Presentation
3 October 2022 Process-aware circuit simulation using machine learning compact models for metal oxide semiconductor capacitors under illumination (Conference Presentation)
Zheng Kai Yang, Ya-Wen Ho, Tejender Rawat, Chung-Yuan Chang, Albert Lin
Author Affiliations +
Abstract
Machine learning (ML) based compact device modeling provides the opportunity for process-aware device modeling and thus process-aware circuit simulation. In contrast, incorporating semiconductor manufacturing parameters into compact models (CM) and subsequent circuit simulations using pure physics-based CM is difficult. We demonstrate process-aware circuit simulation where the effect of plasma treatment and thermal annealing can be directly reflected on the circuit output in SPICE transient simulation. The Verilog-A model input is V, frequency(f), area(A), and process conditions, i.e., plasma surface treatment (PST) and post-metal annealing (PMA). The MOSCAP capacitance-voltage (CV) characteristics under illumination are described by ML compact models.
Conference Presentation
© (2022) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Zheng Kai Yang, Ya-Wen Ho, Tejender Rawat, Chung-Yuan Chang, and Albert Lin "Process-aware circuit simulation using machine learning compact models for metal oxide semiconductor capacitors under illumination (Conference Presentation)", Proc. SPIE 12227, Applications of Machine Learning 2022, 122270M (3 October 2022); https://doi.org/10.1117/12.2632334
Advertisement
Advertisement
KEYWORDS
Device simulation

Machine learning

Capacitors

Metals

Oxides

Semiconductors

Instrument modeling

RELATED CONTENT

Study of a second order low pass filter based on...
Proceedings of SPIE (March 19 2013)
Simulation of GaN/InGaN micro-ring light-emitting devices
Proceedings of SPIE (April 28 2005)
Simulation of spin MOSFETs
Proceedings of SPIE (September 15 2011)

Back to Top