Architectures and design techniques for real-time image processing

Peter A. Ruetz

doi:10.1117/12.19563

1 July 1990 Architectures and design techniques for real-time image processing

Peter A. Ruetz

Proceedings Volume 1246, Parallel Architectures for Image Processing; (1990) https://doi.org/10.1117/12.19563
Event: Electronic Imaging: Advanced Devices and Systems, 1990, Santa Clara, CA, United States

Abstract

In this paper some of the techniques that have been been employed in the design of a set of high performance (20- 40 MHz) DSP standard products 1,2 are discussed. To support real-time operation, each device has an architecture that is dedicated to the function being performed. The chip set includes video line delays, a 64-tap 12-bit rank value filter, a 1024-tap binary template matcher, a 64-tap 8-bit FIR filter, a 9-tap 60 MHz FIR filter, a histogram and Hough transform processor, an FFT chip set and an object contour tracer.

Citation Download Citation

Peter A. Ruetz "Architectures and design techniques for real-time image processing", Proc. SPIE 1246, Parallel Architectures for Image Processing, (1 July 1990); https://doi.org/10.1117/12.19563

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