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30 April 2023 Extending design technology co-optimization from technology launch to HVM
Le Hong, Fan Jiang, Yuansheng Ma, Srividya Jayaram, Joe Kwan, Haizhou Yin, Xiaoyuan Qi, Junjiang Lei
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Proceedings Volume 12495, DTCO and Computational Patterning II; 124950G (2023) https://doi.org/10.1117/12.2658652
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States
Abstract
Modern semiconductor design to fabrication process mainly relies on intra-module validation mechanism to prevent the propagation of systematic defects, such as DRC signing off physical design, OPC Verification validating OPC solution, metrology and inspection gauging the process, and physical failure analysis confirmation of electrical diagnosis. The inter-module information exchange and co-optimization typically happen during the early process and technology development stage via Design-Technology Co-optimization (DTCO). Later into the advanced node’s lifecycle, such co-optimization is facilitated by traditional techniques like Design For Manufacturability (DFM) and Litho Friendly Design (LFD). This talk will present methodologies and infrastructure necessary to feed pre-silicon design data and intelligence forward into the manufacturing process and feed manufacturing information back, post-silicon, to inform the design process.
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Le Hong, Fan Jiang, Yuansheng Ma, Srividya Jayaram, Joe Kwan, Haizhou Yin, Xiaoyuan Qi, and Junjiang Lei "Extending design technology co-optimization from technology launch to HVM", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950G (30 April 2023); https://doi.org/10.1117/12.2658652
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KEYWORDS
Manufacturing
Analytics
Design for manufacturability
Failure analysis
Optical proximity correction
Design for manufacturing
Inspection
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