Paper
13 August 1993 1.8-inch poly-Si TFT-LCDs with novel TFT structure and storage capacitance arrangement
Takashi Sugawara, Kazuhiro Kobayashi, Hiroyuki Murai, Christiaan Baert, Takao Sakamoto, Hidetada Tokioka, Yuichi Masutani, Hirofumi Namizaki, Masahiro Nunoshita
Author Affiliations +
Proceedings Volume 1911, Liquid Crystal Materials, Devices, and Applications II; (1993) https://doi.org/10.1117/12.151214
Event: IS&T/SPIE's Symposium on Electronic Imaging: Science and Technology, 1993, San Jose, CA, United States
Abstract
We have fabricated 1.8-inch and 86,400-pixel poly-Si TFT-LCDs with a novel TFT structure and a storage capacitance (Cst) arrangement. The TFTs have a self-aligned offset structure which is made by a simple process without using an additional mask. With this structure, we have reduced the OFF current, and hence, attained a high ON/OFF current ratio of 107. A novel Cst line arrangement called 'modified Cst on gate' was adopted. Gate lines and Cst lines are arranged alternatively, and the (n-1)-th Cst line is connected to the n-th gate line at the line's end. The Cst line works as redundancy of the gate line. Consequently, we have obtained TFT arrays with no line-defects (240 gate lines). By using these techniques, we have succeeded in fabricating a high-performance 1.8-inch poly-Si TFT-LCD panel for a projection TV.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Takashi Sugawara, Kazuhiro Kobayashi, Hiroyuki Murai, Christiaan Baert, Takao Sakamoto, Hidetada Tokioka, Yuichi Masutani, Hirofumi Namizaki, and Masahiro Nunoshita "1.8-inch poly-Si TFT-LCDs with novel TFT structure and storage capacitance arrangement", Proc. SPIE 1911, Liquid Crystal Materials, Devices, and Applications II, (13 August 1993); https://doi.org/10.1117/12.151214
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KEYWORDS
Capacitance

Electrodes

Resistance

Plasma

Silicon

Etching

Fabrication

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