Practical manufacturing technique for reducing charge-induced gate oxide degradation during ion implantation

Kenneth G. Moerschel; W. A. Possanza; James Sung; M. A. Prozonic; T. Long; J. Pavlo; T. Chrapacz

doi:10.1117/12.361350

27 August 1999 Practical manufacturing technique for reducing charge-induced gate oxide degradation during ion implantation

Kenneth G. Moerschel, W. A. Possanza, James Sung, M. A. Prozonic, T. Long, J. Pavlo, T. Chrapacz

Author Affiliations +

Proceedings Volume 3884, In-Line Methods and Monitors for Process and Yield Improvement; (1999) https://doi.org/10.1117/12.361350
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

Test wafers were fabricated to evaluate leakage and charge-to- breakdown (Q_bd) of gate oxide capacitor structures subjected to high dose ion implantation. Both insulating and partially conductive (polysilicon) films were present on the wafer backsides during implantation, and the ion implanter's electron flood gun current was varied to optimize the final capacitor leakage yield. Relative to a conductive (polysilicon) backside film present during ion implantation, a backside 1700 Angstrom LPCVD Si₃N₄ layer provided significantly improved gate oxide protection, after optimization of the electron flood gun current. The backside LPCVD Si₃N₄ had no discernible effect on the Q_bd of the capacitors after high dose ion implantation.

Citation Download Citation

Kenneth G. Moerschel, W. A. Possanza, James Sung, M. A. Prozonic, T. Long, J. Pavlo, and T. Chrapacz "Practical manufacturing technique for reducing charge-induced gate oxide degradation during ion implantation", Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); https://doi.org/10.1117/12.361350

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