Noise analysis of MESFET gallium arsenide circuits

Kamran Eshraghian; Hans-Joerg Pfleiderer; Stefan W. Lachowicz

doi:10.1117/12.368424

8 October 1999 Noise analysis of MESFET gallium arsenide circuits

Kamran Eshraghian, Hans-Joerg Pfleiderer, Stefan W. Lachowicz

Proceedings Volume 3893, Design, Characterization, and Packaging for MEMS and Microelectronics; (1999) https://doi.org/10.1117/12.368424
Event: Asia Pacific Symposium on Microelectronics and MEMS, 1999, Gold Coast, Australia

Abstract

There are numerous sources of noise present in the VLSI integrated circuits. A function that can measure the ability of a digital logic circuit to operate error-free in a noisy environment is noise margin which can be define in several ways from the transfer characteristic of the logic circuit. It is critical to be able to precisely evaluate a noise margin for Gallium Arsenide circuits, as its value is usually limited to the extent that only NOR gates are allowed in DCFL digital circuits and NAND gates, where stacked pull down transistors would be required, are excluded. In the paper, the best-case and worst-case static noise margin are discussed and it is shown that not only the load but also the noise voltage has to be included when evaluating a transfer function. Fortunately, the best-case noise margin can still be calculated with the nose free transfer function. But the more useful worst-case noise margin is shown to depend on the transfer function including the noise source. Therefore, as was already pointed out by Lohstroh for CMOS circuits, the best way to calculate the noise margin is to start a quasi-static transient simulation with all noise sources being zero and by increasing the amplitudes of the noise sources slowly compared to the switching speed of the logic circuits. The worst-case noise margin is then found as the noise amplitude at which the chain exhibits a malfunction. Since an infinitely long chain is sown to be equivalent to a flip-flop the flip-flop can be used for the simulation instead. The examples of an inverter and an AND gate illustrate the theory presented.

Citation Download Citation

Kamran Eshraghian, Hans-Joerg Pfleiderer, and Stefan W. Lachowicz "Noise analysis of MESFET gallium arsenide circuits", Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); https://doi.org/10.1117/12.368424

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KEYWORDS

Gallium arsenide

Logic

Digital electronics

Transistors

Field effect transistors

Switching

Digital electronic circuits

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