New clear-out scheme to improve the overlay performance for a CMP process

Yao-Wen Guo; Han-Pin Kao; Tsung-Chih Chien; Chiafu Chang; Hsin-Sung Lin; Yen-Fen Chen; Chin-Yu Ku

doi:10.1117/12.473432

16 July 2002 New clear-out scheme to improve the overlay performance for a CMP process

Yao-Wen Guo, Han-Pin Kao, Tsung-Chih Chien, Chiafu Chang, Hsin-Sung Lin, Yen-Fen Chen, Chin-Yu Ku

Proceedings Volume 4689, Metrology, Inspection, and Process Control for Microlithography XVI; (2002) https://doi.org/10.1117/12.473432
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

To obtain good overlay performance, the quality of the wafer marks should be well designed. Although different brands of steppers and scanners use unique mark pattern design and alignment system, these exposure tools determine the position of marks through the signal obtaining from the height difference within the mark region. The largest problem of the marks is that the quality of the marks is influenced by the process conditions, such as film deposition, chemical mechanical polishing, and etching conditions, etc. In this work, we studied the impact of the CMP on the quality of the ASML alignment mark. The film structure and process flow are also investigated to understand the deformation of marks for different clear-out scheme. The lot-to-lot overlay variation can be prevented when the new clear-out scheme is employed.

Citation Download Citation

Yao-Wen Guo, Han-Pin Kao, Tsung-Chih Chien, Chiafu Chang, Hsin-Sung Lin, Yen-Fen Chen, and Chin-Yu Ku "New clear-out scheme to improve the overlay performance for a CMP process", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473432

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