Flash memory-cell characterization using two-transistor cell compact macro-model for system-on-chip design

Changyuan Chen; Samar Saha

doi:10.1117/12.601974

17 May 2005 Flash memory-cell characterization using two-transistor cell compact macro-model for system-on-chip design

Changyuan Chen, Samar Saha

Proceedings Volume 5755, Data Analysis and Modeling for Process Control II; (2005) https://doi.org/10.1117/12.601974
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

In this paper, we present a systematic methodology to extract two-transistor split-gate flash memory cell model for an accurate DC simulation of SoC designs. Since measured device characteristics require re-design of test-structures with FG contacts, we have used a technology CAD (TCAD) based methodology to develop 2T-cell models for sub-0.18 μm split gate flash memory cells.

Citation Download Citation

Changyuan Chen and Samar Saha "Flash memory-cell characterization using two-transistor cell compact macro-model for system-on-chip design", Proc. SPIE 5755, Data Analysis and Modeling for Process Control II, (17 May 2005); https://doi.org/10.1117/12.601974

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