Partitioning and characterization of high speed adder structures in deep-submicron technologies

Adrián Estrada; Gashaw Sassaw; Carlos J. Jiménez; Manuel Valencia

doi:10.1117/12.721996

10 May 2007 Partitioning and characterization of high speed adder structures in deep-submicron technologies

Adrián Estrada, Gashaw Sassaw, Carlos J. Jiménez, Manuel Valencia

Proceedings Volume 6590, VLSI Circuits and Systems III; 659004 (2007) https://doi.org/10.1117/12.721996
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

The availability of higher performance (in area, time and power consumption) and greater precision binary adders is a constant requirement in digital systems. Consequently, the design and characterization of adders and, most of all, their adaptation to the requisites of present-day deep-submicron technologies, are today still issues of concern. The binary adder structures in deep-submicron technologies must be revised to achieve the best balance between the number of bits in the adder and its delay, area and power consumption. It is therefore very important to make an effort to carefully optimize adder structures, thus obtaining improvements in digital systems. This communication presents the optimization of adder structures for implementations in deep-submicron technologies through their partitioning into blocks. This partitioning consists of dividing the number of input bits to the adder into several subsets of bits that will constitute the inputs to several adder structures of the same or of different types. The structures used to accomplish this study range from the more traditional types, such as the carry look ahead adder, the ripple carry adder or the carry select adder, to more innovative kinds, like the parallel prefix adders of the type proposed by Brent-Kung, Han-Carlson, Kogge-Stone or Ladner-Fischer. The analyses carried out allow the characterization of structures implemented in deep-submicron technologies for area, delay and power consumption parameters.

Citation Download Citation

Adrián Estrada, Gashaw Sassaw, Carlos J. Jiménez, and Manuel Valencia "Partitioning and characterization of high speed adder structures in deep-submicron technologies", Proc. SPIE 6590, VLSI Circuits and Systems III, 659004 (10 May 2007); https://doi.org/10.1117/12.721996

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available