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Semiconductor manufacturing technology has shifted towards finer design rules, and demands for
critical dimension uniformity (CDU) of resist patterns have become greater than ever.
One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB)
temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and
PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of
within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes
to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU,
etcher-specific CD variation needs to be controlled.
In this evaluation,
1. We verified whether etcher-specific CD variation can be controlled and consequently Etching
Pattern CDU can be further improved by controlling resist patterns through PEB control.
2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in
wiring resistance variation.
The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared.
2. Resist patterns were created on them.
3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning
off the resist and BARC, CD of etched D-Poly was measured.
4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer
temperature distribution in the PEB process was modified.
5. Resist patterns were created again, followed by the second etching and cleaning, which was
followed by CD measurement.
We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as
OCD is minimally affected by Line Edge Roughness (LER).
As a result,
1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in
etcher-specific CD variation and the improvement in Etching Pattern CDU.
2. The improvement in Etching Pattern CDU has an effect on the reduction in wiring resistance
variation.
The method for Etching Pattern CDU improvement through PEB control reduces within-wafer
variation of MOS transistor's gate length. Therefore, with this method, we can expect to observe uniform
within-wafer MOS transistor characteristics.
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