Paper
1 April 2008 Patterning strategy and performance of 1.3NA tool for 32nm node lithography
Shoji Mimotogi, Masaki Satake, Yosuke Kitamura, Kazuhiro Takahata, Katsuyoshi Kodera, Hiroharu Fujise, Tatsuhiko Ema, Koutaro Sho, Kazutaka Ishigo, Takuya Kono, Masafumi Asano, Kenji Yoshida, Hideki Kanai, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Katsura Miyashita, Soichi Inoue
Author Affiliations +
Abstract
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shoji Mimotogi, Masaki Satake, Yosuke Kitamura, Kazuhiro Takahata, Katsuyoshi Kodera, Hiroharu Fujise, Tatsuhiko Ema, Koutaro Sho, Kazutaka Ishigo, Takuya Kono, Masafumi Asano, Kenji Yoshida, Hideki Kanai, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Katsura Miyashita, and Soichi Inoue "Patterning strategy and performance of 1.3NA tool for 32nm node lithography", Proc. SPIE 6924, Optical Microlithography XXI, 69240M (1 April 2008); https://doi.org/10.1117/12.772201
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Cited by 4 scholarly publications.
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KEYWORDS
Lithography

Optical lithography

Scanners

Semiconducting wafers

SRAF

Lithographic illumination

Metals

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