Paper
25 March 2010 Evolution of thermal cure resist for double patterning applications
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Abstract
To extend immersion based lithography to below 32nm half pitch, the implementation of Double-Patterning lithography requires that cost be contained by as many means possible. In addition to CDU and defectivity, simplifying the process flow is a viable approach to helping accomplish cost containment. For Litho-Litho-Etch processes, this entails replacing the flows that require spin-on chemical freeze with a solely thermally cured resist approach, thereby eliminating materials and several process steps from the flow. As part of ongoing efforts to allow Double-Patterning techniques to further scale semiconductor devices, we use DETO (Double-Expose-Track-Optimized) methods for producing pitch-split patterns capable of supporting 16 and 11-nm node semiconductor devices. In this paper we present the assessment from a series of thermal cure double-patterning resist systems; with a focus on process latitude, CDU, and resolution limit.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Reilly, Young C. Bae, Vaishali Vohra, Chiew-Seng Koay, and Matthew Colburn "Evolution of thermal cure resist for double patterning applications", Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 76392W (25 March 2010); https://doi.org/10.1117/12.846748
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KEYWORDS
Double patterning technology

Lithography

Photoresist processing

Semiconducting wafers

Electroluminescence

Astatine

Etching

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