Nios II hardware acceleration of the epsilon quadratic sieve algorithm

Uwe Meyer-Bäse; Guillermo Botella; Encarnacion Castillo; Antonio García

doi:10.1117/12.849883

12 April 2010 Nios II hardware acceleration of the epsilon quadratic sieve algorithm

Uwe Meyer-Bäse, Guillermo Botella, Encarnacion Castillo, Antonio García

Proceedings Volume 7703, Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII; 77030M (2010) https://doi.org/10.1117/12.849883
Event: SPIE Defense, Security, and Sensing, 2010, Orlando, Florida, United States

Abstract

The quadratic sieve (QS) algorithm is one of the most powerful algorithms to factor large composite primes used to break RSA cryptographic systems. The hardware structure of the QS algorithm seems to be a good fit for FPGA acceleration. Our new ε-QS algorithm further simplifies the hardware architecture making it an even better candidate for C2H acceleration. This paper shows our design results in FPGA resource and performance when implementing very long arithmetic on the Nios microprocessor platform with C2H acceleration for different libraries (GMP, LIP, FLINT, NRMP) and QS architecture choices for factoring 32-2048 bit RSA numbers.

Citation Download Citation

Uwe Meyer-Bäse, Guillermo Botella, Encarnacion Castillo, and Antonio García "Nios II hardware acceleration of the epsilon quadratic sieve algorithm", Proc. SPIE 7703, Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII, 77030M (12 April 2010); https://doi.org/10.1117/12.849883

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