Sub-20nm logic lithography optimization with simple OPC and multiple pitch division

Michael C. Smayling; Valery Axelrad; Koichiro Tsujita; Hidetami Yaegashi; Ryo Nakayama; Kenichi Oyama; Yuichi Gyoda

doi:10.1117/12.914916

13 March 2012 Sub-20nm logic lithography optimization with simple OPC and multiple pitch division

Michael C. Smayling, Valery Axelrad, Koichiro Tsujita, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, Yuichi Gyoda

Proceedings Volume 8326, Optical Microlithography XXV; 832613 (2012) https://doi.org/10.1117/12.914916
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A line/cut approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm.[1] Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node.[2] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the "cut" patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,4,5] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using simplified OPC beyond 20nm in small steps, eventually reaching the 16nm node. The same "cut" pattern is used for each set of simulations, with "x" and "y" locations for the cuts scaled for each step. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Experimental demonstration of the cut approach using simplified OPC and conventional illuminators will be presented with comparison to the complex OPC result. MEEF can be measured experimentally. Lines were patterned with 193nm immersion with no complex OPC. The final dimensions were achieved by applying pitch division twice.[6] Using the conditions optimized for the logic block, an SRAM block simulation and experimental results will also be presented.

Citation Download Citation

Michael C. Smayling, Valery Axelrad, Koichiro Tsujita, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, and Yuichi Gyoda "Sub-20nm logic lithography optimization with simple OPC and multiple pitch division", Proc. SPIE 8326, Optical Microlithography XXV, 832613 (13 March 2012); https://doi.org/10.1117/12.914916

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