Paper
9 July 2015 Strategy optimization for mask rule check in wafer fab
Chuen Huei Yang, Shaina Lin, Roger Lin, Alice Wang, Rachel Lee, Erwin Deng
Author Affiliations +
Abstract
Photolithography process is getting more and more sophisticated for wafer production following Moore’s law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers’ judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chuen Huei Yang, Shaina Lin, Roger Lin, Alice Wang, Rachel Lee, and Erwin Deng "Strategy optimization for mask rule check in wafer fab", Proc. SPIE 9658, Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII, 96580Y (9 July 2015); https://doi.org/10.1117/12.2192951
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KEYWORDS
Photomasks

Semiconducting wafers

Optical proximity correction

Optical lithography

Double patterning technology

Inspection

Distortion

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