Stress technologies such as stress liners are used to improve the performance of advanced CMOS devices. Due to the contextual situation of a transistor in the physical design layout, unintended stress from neighboring cells can cause variations in the transistor characteristics. This effect is called Layout Dependent Effect (LDE). In this work we propose a fast method to detect outlier transistors due to the LDEs by profiling and sampling them from the VLSI design with millions of transistors and many devices. The proposed method can reduce the TAT for quantitative evaluation of the LDE for design layouts that have not passed the LVS. We also propose a pattern matching based method to search motifs created by encapsulating neighborhood of outlier transistors with large Vth variations. This enables designers to trace such LDE hotspot patterns and thereby outlier transistors during the design phase.
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