Dr. Alejandro Linares-Barranco Profile

Dr. Alejandro Linares-Barranco

Professor at Univ. de Sevilla

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Publications (4)

Proceedings Article | 22 May 2007 Paper

AER image filtering

F. Gómez-Rodríguez, A. Linares-Barranco, R. Paz, L. Miró-Amarante, G. Jiménez, A. Civit

Proceedings Volume 6592, 659207 (2007) https://doi.org/10.1117/12.724216

KEYWORDS: Image filtering, Linear filtering, Computing systems, Field programmable gate arrays, Digital image processing, Image processing, Neurons, Retina, Digital filtering, Frame grabbers

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Proceedings Article | 22 May 2007 Paper

Address-event-based platform for bioinspired spiking systems

A. Jiménez-Fernández, C. Luján, A. Linares-Barranco, F. Gómez-Rodríguez, M. Rivas, G. Jiménez, A. Civit

Proceedings Volume 6592, 659206 (2007) https://doi.org/10.1117/12.724156

KEYWORDS: Field programmable gate arrays, Prototyping, Computing systems, Neurons, Operating systems, Clocks, Telecommunications, Control systems, Signal processing, Receivers

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Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate "events" according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal computer implies to depend on software tools and operating systems that can make the system slower and un-robust. This paper addresses the problem of communicating several AER based chips to compose a powerful processing system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone (independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3 4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps).

Proceedings Article | 29 June 2005 Paper

AER synthetic generation in hardware for bio-inspired spiking systems

Alejandro Linares-Barranco, Bernabe Linares-Barranco, Gabriel Jimenez-Moreno, Anton Civit-Balcells

Proceedings Volume 5839, (2005) https://doi.org/10.1117/12.608192

KEYWORDS: Neurons, Computing systems, Biomimetics, Receivers, Video, Field programmable gate arrays, Data communications, Human-machine interfaces, Receptors, MATLAB

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Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses a Spartan II 200 FPGA. This system for AER Synthetic Generation is capable of transforming frames of 64x64 pixels, received through a standard computer PCI bus, at a frame rate of 25 frames per second, producing spike events at a peak rate of 10⁷ events per second.

Proceedings Article | 29 June 2005 Paper

Time-recovering PCI-AER interface for bio-inspired spiking systems

R. Paz-Vicente, A. Linares-Barranco, D. Cascado, S. Vicente, G. Jimenez, A. Civit

Proceedings Volume 5839, (2005) https://doi.org/10.1117/12.608255

KEYWORDS: Human-machine interfaces, Receivers, Neurons, Computing systems, Clocks, Biomimetics, Data communications, MATLAB, Telecommunications, Field programmable gate arrays

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