Work is focused on the study and control of anisotropic silicon etching profiles by using conventional room temperature RIE system with SF6/O2 chemistry. The main process parameters of etching are considered in order to achieve high etching rate, high anisotropy, high aspect ratio, good selectivity, and all this achieved with good homogeneity and repeatability. High anisotropic etching profile, resulting in undercut less than 1.5 μm, aspect ratio higher than 10 and selectivity to oxide of 80 are obtained for 40 μm depth and 3.5 μm wide squared etched pillars. We determined that 29 % content of oxygen in total gas flow is optimal. Silicon and oxide etching rate and selectivity in dependence of total gas flow and gas flow ratio were investigated. Typically, silicon etching rate of 1.6 μm/min, oxide etching rate of 20 nm/min and selectivity of 80 were obtained. Due to the effect of load dependency of etching process, empirical dependence between load and etching rate was determined. Positive RIE lag is observed at etching high aspect ratio trenches. Etched trenches of 6 μm width (aspect ratio less than 7) revealed negligible influence of pressure on aspect ratio dependent etching, for etching performed at pressure 60 or 100 mtorr.
Silicon crystal planes that can be potentially used as optical mirrors for deflecting light beams from/to optical fibres aligned in grooves were investigated. Aligning grooves and passive mirror-like planes were formed by wet micromachining in KOH and TMAH etchants with addition of additives such as IPA and Triton surfactant. On (100) silicon, {111}, {110}, {311} mirror planes were realized, while on (110) silicon, {010} and {111} mirror planes were demonstrated for the chosen mask orientation. Characterization of passive mirrors with 632nm incident light was performed by measuring angles and specific shape patterns of reflected light beams and by determination of light scattering due to mirror microroughness. Results show that {111} planes exhibit better surface quality compared to {110} mirrors and lowest scattering, however the reflected angle is 54,74° on (100) silicon. On (110) silicon the 45° reflection angle with {010} crystal planes is obtained by proper mask alignment with very small scattering angle below 3°. For reflecting the beam with 1,33 μm wavelength, sputtered layer of aluminum is used as reflecting coating on silicon mirrors, increasing the reflectivity by 24%.
This paper presents an investigation focused on the formation of (311) planes by wet anisotropic etching of (100) silicon in 5% TMAH etchant. Atomistic model of (311) plane formation is proposed, suggesting that (311) planes are composed of (111) and (100) steps. Surface roughness that is in most cases consequence of hillock formation at low concentrations of TMAH and etch rates of (311) and (100) planes were studied as a function of etch temperature, time and addition of small amounts of ammonium peroxodisulfate (APODS). It was found that the smooth (311) planes without hillocks can be obtained only by etching in 5% TMAH with addition of 0,5% APODS. Due to obvious decomposition of APODS in the etching process determined by increased surface roughness, replenishing of additive is mandatory. Stirring experiments with 5%TMAH solution showed increased surface roughness and reduced etch rates of (100) and (311) plane. Dissolution rates of thermal oxide, LPCVD nitride and PECVD oxide and nitride were determined in temperature range from 60 degree(s)C-90 degree(s)C in 5% TMAH. APODS additive was found to have minor influence.
A conventional pn diffused junction silicon photodiode originally developed for visible and near infrared light was optimized for ultraviolet wavelength spectrum. Optimization was performed with numerical simulation tools and experimental work. The results of modeling and experiment are compared and discussed. MOS capacitor was integrated on active region of photodiode in order to control the quality of fabricated surface passivation layer. p+n junction structure and antireflective coating have been identified as two most important design and processing steps.
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