L. Lodola, L. Ratti, D. Comotti, L. Fabris, M. Grassi, P. Malcovati, M. Manghisoni, V. Re, G. Traversi, C. Vacchi, G. Batignani, S. Bettarini, F. Forti, G. Casarosa, F. Morsani, A. Paladino, E. Paoloni, G. Rizzo, M. Benkechkache, G.-F. Dalla Betta, R. Mendicino, L. Pancheri, G. Verzellesi, H. Xu
The PixFEL collaboration has developed the building blocks for an X-ray imager to be used in applications at FELs. In particular, slim edge pixel detectors with high detection efficiency over a broad energy range, from 1 to 12 keV, have been developed. Moreover, a multichannel readout chip, called PFM2 (PixFEL front-end Matrix 2) and consisting of 32 × 32 cells, has been designed and fabricated in a 65 nm CMOS technology. The pixel pitch is 110 μm, the overall area is around 16 mm2. In the chip, different solutions have been implemented for the readout channel, which includes a charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper and an A-to-D converter with a 10 bit resolution. The CSA can be configured in four different gain modes, so as to comply with photon energies in the 1 to 10 keV range. The paper will describe in detail the channel architecture and present the results from the characterization of PFM2. It will discuss the design of a new version of the chip, called PFM3, suitable for post-processing with peripheral, under-pad through silicon vias (TSVs), which are needed to develop four-side buttable chips and cover large surfaces with minimum inactive area.
Cross-talk characterization results of high-fill-factor single-photon avalanche diode (SPAD) arrays in CMOS 150-nm technology are reported and discussed. Three different SPAD structures were designed with two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1, and 1.6 μm). Each SPAD was implemented in an array, composed of 25 (5×5) devices, which can be separately activated. Measurement results show that the average cross-talk probability is well below 1% for the shallow-junction SPAD structure with 15.6 μm pitch and 39.9% fill factor, and 1.45% for the structure with 25.6 μm pitch and 60.6% fill factor. An increase of cross-talk probability with the excess bias voltage is observed.
The characterization of two Single-Photon Avalanche Diodes (SPADs) structures fabricated in CMOS 150nm technology is reported in this paper. The structures are based on a pwell/n-iso junction and differ only for the presence of a polysilicon layer above the guard ring. Each structure is implemented in two different shapes (circular and square) and four sizes (5,10,15 and 20μm). Measurement results show that both average breakdown voltage and non-uniformity decrease with SPAD sizes. The statistical variation of Photon Detection Efficiency (PDE) and its dependence on device size are also reported and discussed. For all the considered device sizes, a PDE non-uniformity lower than 0.5% was measured.
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