Mr. Igor Jekauc Profile

Igor Jekauc

Process Engineer

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Publications (9)

Proceedings Article | 10 May 2005 Paper

Metal etcher qualification using angular scatterometry

Igor Jekauc, Jasen Moffitt, Sushil Shakya, Elizabeth Donohue, Prasad Dasari, Christopher Raymond, Mike Littau

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598828

KEYWORDS: Semiconducting wafers, Etching, Metals, Scatterometry, Polymers, Profilometers, Scanning electron microscopy, Critical dimension metrology, Metrology, Tin

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Proceedings Article | 28 May 2004 Paper

Aberration measurement and matching: a correlation of measurement technique and dedication scheme implications

William Roberts, Igor Jekauc

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535288

KEYWORDS: Overlay metrology, Manufacturing, Lens design, Scanners, Front end of line, Distortion, Critical dimension metrology, Semiconductor manufacturing, Optical alignment

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Proceedings Article | 28 May 2004 Paper

Minimizing critical layer systematic alignment errors during non-dedicated processing

Igor Jekauc, William Roberts

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535248

KEYWORDS: Overlay metrology, Data modeling, Optical alignment, Performance modeling, Manufacturing, Tolerancing, Optical lithography, Process control, Semiconducting wafers, Lithography

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For the 150 nm and smaller half-pitch geometries, many DRAM manufacturers frequently employ dedicated exposure tool strategy for processing of most critical layers. Individual die tolerances of less than 40 nm are not uncommon for such compact geometries and a method is needed to reduce systematic overlay errors. The dedication strategy relies on the premise that a component of the systematic error induced by the inefficiencies in the exposure tool encountered at a specific layer can be diminished by re-exposing subsequent layer(s) on the same tool thus canceling out a large component of this error. In the past this strategy has, in general, resulted in better overall alignment performance, better exposure tool modeling and in decreased residual modeling errors. Increased alignment performance due to dedication does not come without its price. In such a dedicated strategy wafers are committed to process on the same tool at subsequent lithographic layers thus decreasing manufacturing flexibility and in turn affecting cost through increased processing cycle time. Tool down-events and equipment upgrades requiring significant downtime can also have a significant negative impact on running of a factory. This paper presents volume results for the 140 nm and 110 nm half-pitch geometries using 248 nm and 193 nm respective exposure wavelength state-of-art systems that show that dedicated processing still produces superior overlay and device performance results when compared blindly against non-dedicated processing. Results are also shown that at a given time an acceptable match may be found producing near equivalent results for non-dedicated processing. Changes in alignment capability are also observed after major equipment maintenance and component replacement. A point-in-time predictor strategy utilizing residual modeling errors and a set of modified performance specifications is directly compared against measured overlay data after patterning, against within field AFOV measurements after etching of the pattern and to final device performance.

Proceedings Article | 24 May 2004 Paper

Enhancing film thickness metrology optical coefficient control

Igor Jekauc, Elizabeth Donohue, Bill Roberts

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535231

KEYWORDS: Metrology, Semiconducting wafers, Dielectrics, Refractive index, Time metrology, Process control, Control systems, Lithography, Critical dimension metrology, Optical testing

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Due to necessities of semiconductor manufacturing some of the most critical lithographic layers may utilize only dielectric anti-reflection coatings (DARC) and not the organic anti-reflective coatings in order to minimize substrate effects on critical dimension (CD) control and in order to position the process at a best possible node. As a result of this relationship, stricter limits of control of index of refraction and extinction coefficient are generally imposed on the DARC process. While the DARC process may utilize a gas flow adjustment in order to control the optical constants, one of the biggest obstacles becomes the film thickness metrology, which is most often used via either the Bruggeman or the Harmonic Oscillator models to measure the desired optical coefficients. Unfortunately, the control of optical properties to within a few percent is generally outside of the window of specifications of even the latest generation of film thickness metrology tools. Furthermore, with each subsequent exposure node, the wavelength of interest for the optical coefficients is also near the limit of the lamp or radiation source on the film thickness metrology tool thus creating additional noise and measurement instability. An interesting situation is depicted in this paper where the metrology variation in measurement of the optical coefficients for a single stack DARC film is greater than the variation of twenty process chambers. The metrology variation was confined in major part to consist of tool-to-tool variation and of tool changes after any work on the ellipsometer. A systematic way of reducing this measurement variation is presented which allows for introduction of a floating standard tied to the combined average performance of all metrology tools without necessarily using a golden tool or a golden set of wafers. At the same time, offsets are applied to each metrology tool thus ensuring a much tighter population. Although the described situation is not ideal, with the current specifications on measurement of optical coefficients it is one of few methodologies necessary for adequate process control without the expenditure for a new toolset.

Proceedings Article | 24 May 2004 Paper

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

Bill Roberts, Cort Demmert, Igor Jekauc, Jason Tiffany

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.535323

KEYWORDS: Semiconducting wafers, Yield improvement, Etching, Sensors, Lithography, Wafer-level optics, Overlay metrology, Chemical mechanical planarization, Optical alignment, Process control

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Proceedings Article | 14 May 2004 Paper

Necessity of chemical edge bead removal in modern day lithographic processing

Igor Jekauc, Michael Watt, Trip Hornsmith, Jason Tiffany

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.535268

KEYWORDS: Semiconducting wafers, Lithography, Coating, High speed cameras, Contamination, Photoresist processing, Tolerancing, Wafer-level optics, Yield improvement, Semiconductors

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Some form of edge bead removal (EBR) is one of the standard requirements for a lithographic process. Without any intervention, resist may accumulate at the edge of the wafer at up to several times the nominal thickness of the resist. In addition to this edge bead, the resist is likely to wrap around the wafer contaminating the backside of the wafer as well. It’s needless to say that such a condition would present a significant contamination risk not only for the resist track and the exposure tool but for process equipment outside of lithography as well. Two not necessarily exclusive strategies have been used in the past for edge bead removal. One is topside chemical EBR where solvent is dispensed on the edge of the wafer as the wafer is rotated immediately after coating, and the other method is where a ring of exposed resist is formed by subjecting the resist on the outer edges of the wafer to a broadband exposure; also know as wafer-edge exposure (WEE). The advantage of the chemical method is that it will remove the photo resist but also the organic anti-reflective coating (ARC), which is not photosensitive. The disadvantage of this method is obvious as any latitude in tool tolerances or imperfections on the wafer will result in solvent dispense to the undesirable areas of the wafer. While the optical method is much cleaner, its main disadvantage is that it will not remove ARC. As the feature size and die size shrink, there is less and less repairable redundancy on modern semiconductor chips. An observed effect in our manufacturing facility has been an increased sensitivity to tool imperfections and a quantifiable level of yield loss due to solvent splashing for the 140nm generation. Accounting for the fact that the ARC layer is generally an order of magnitude thinner than the resist layer, yield-maximizing setup of edge bead removal for one lithographic layer and complete removal of topside chemical EBR is discussed in detail in this paper as well as the extension of the same principle to maximize yield at other layers.

Proceedings Article | 29 April 2004 Paper

Necessary nonzero lithography overlay correctables for improved device performance for 110nm generation and lower geometries

Igor Jekauc, Bill Roberts, Paul Young, Paul Jowett, Reuben Ferguson, Sean Louks

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.535258

KEYWORDS: Optical alignment, Overlay metrology, Lithography, Semiconducting wafers, Metrology, Etching, Metals, Chemical mechanical planarization, Composites, Yield improvement

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Proceedings Article | 29 April 2004 Paper

Complementary feed-forward and feedback method for improved critical dimension control

Igor Jekauc, Christopher Gould, Walter Hartner, Tim Urenda

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.535204

KEYWORDS: Critical dimension metrology, Control systems, Error analysis, Metrology, Semiconducting wafers, Feedback control, Lithography, Process control, Cadmium, Photoresist materials

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Proceedings Article | 14 September 2001 Paper

Mask error factor: critical dimension variation across different tools, features, and exposure conditions

Igor Jekauc, William Roberts, Christine Hampe

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435784

KEYWORDS: Photomasks, Semiconducting wafers, Reticles, Image quality, Critical dimension metrology, Objectives, Cadmium, Imaging systems, Wafer-level optics, Resolution enhancement technologies

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Showing 5 of 9 publications

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