Autostereoscopic displays in fact show many views of the object of interest simultaneously. These individual views have
to be re-shuffled to fit the final display. This composition task is usually done as an off-line process. We present in this
paper a flexible pixel compositor that bridges the image generator (e.g., a rendering cluster) and the final display devices
(such as a set of over-lapping projectors to form an ultra-high-resolution display). Our compositor is capable of
performing an arbitrary mapping of pixels from any input frame to any output frame, and executing typical composition
operations (e.g., blending) at the same time. To the best of our knowledge, our design is the only compositor that allows
non-block based per-pixel warping and composition. This is particularly important for lenticular displays in which the
different views have to be interleaved in the frame buffer. In this paper, we present an initial hardware prototype and
some preliminary results in the firmware development.
A new high-performance scalable systolic array processor architecture module for implementation of the two-dimensional discrete convolution algorithm on an (i×j) pixel input image plane (IP) using an (n×n) filter coefficient (FC) plane is first presented. The module generates one convoluted output image (OI) plane pixel per system clock cycle for an (n×n) FC plane using a level of r hardware resources. Second, the architecture is extended in a modular scalable manner to allow simultaneous convolution of a single IP, with k different (n×n) FC planes, such that k convoluted OI plane pixels are generated each system clock cycle, utilizing less than (k*r) hardware resources. The new convolution architecture may be implemented to an ASIC or programmable logic device (PLD) platform. Results of synthesizing and implementing the proposed architecture are shown, illustrating the scalability of the new convolution architecture relative to k. Results from postimplementation virtual hardware prototype simulation testing and from testing a PLD-based experimental hardware prototype are shown that validate correct functional and performance operation of the new convolution architecture module.
A new high-performance scalable systolic array processor architecture module is presented which can simultaneously convolute k different (n x n) Filter Coefficient (FC) planes with a single (i x j) pixel Input Image Plane (IP). The architecture will have the capability to simultaneously perform convolution of k different (n x n) FC planes on 600dpi (dot per inch) IPs of size 8½” x 11” at a rate such that k convoluted Output Image (OI) plane pixels are output each system clock cycle for a system clock cycle time of less than 10 nanoseconds. Bit-parallel arithmetic is used and each IP pixel is 8-bits in length and each FC plane coefficient is 6-bits in length. A new pipelined systolic type architecture module is first developed which can generate one convoluted OI plane pixel per system clock cycle using a level of 'r' hardware resources for the case of (n = 5). The architecture is then extended in a scalable and deeper pipelined manner to allow simultaneous convolution of a single IP pixel, with k different (n×n) FC planes for the case of (n = 5), within one system clock cycle, utilizing less than (k × r) hardware resources. Synthesis and post-implementation VHDL simulation results are shown for an experimental model of the architecture which validates the scalability and functionality of the architecture. Simulation results demonstrate the performance of the architecture to be directly proportional to pipeline depth.
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