KEYWORDS: Image classification, Library classification systems, Databases, Logic, Metals, Standards development, Front end of line, Back end of line, Design for manufacturing
As technology advances, chip size becomes larger and larger, this brings challenges when engineers would like to do a quick investigation of the design in a short time, like hotspot detection and layout fixing. An idea to mitigate the challenges is to decompose a layout into patterns and classify these patterns to unique ones. Engineers then prioritize their work on these unique patterns. Patterns from different products can be accumulated and recorded, when a new design comes in, the known patterns will be filtered out from all unique patterns seen in this new design. When the pattern database is large enough and contains enough safe and weak patterns, machine learning can be used to train the algorithm to predict hotspots in the new design. The key point is how to efficiently decompose a layout and group those patterns. This paper presents how to decompose a layout by using Calibre Pattern Matching and DRC. The experiment data shows that this is a very efficient way to decompose a layout automatically.
As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.
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