In the past years, EUV lithography scanner systems have entered high-volume manufacturing for state-of-the-art integrated circuits (IC), with critical dimensions down to 10 nm. This technology uses 13.5-nm EUV radiation, which is transmitted through a near-vacuum H2 background gas, imaging the pattern of a reticle onto a wafer. The energetic EUV photons excite the background gas into a low-density H2 plasma. The resulting plasma will locally change the near-vacuum into a conducting medium and can charge floating surfaces and particles, also away from the direct EUV beam. We will discuss the interaction between EUV-induced plasma and electrostatics, by modeling and experiments. We show that the EUV-induced plasma can trigger discharges well below the classical Paschen limit. Furthermore, we demonstrate the charging effect of the EUV plasma on both particles and surfaces. Uncontrolled, this can lead to unacceptably high voltages on the reticle backside and the generation and transport of particles. We demonstrate a special unloading sequence to use the EUV-induced plasma to actively solve the charging and defectivity challenges.
With the introduction of the NXE:3400B scanner, ASML has brought EUV to High-Volume Manufacturing (HVM). In this context, ASML is pursuing a dual-path approach towards zero reticle defectivity: EUVcompatible pellicle or zero particles towards reticle by advanced particle contamination control. This paper will focus primarily on the approach of advanced particle contamination control and on the understanding of EUV-induced plasma to control both release and transport of particles within the scanner. This paper will present our advancements in understanding and control of particle forces related to the EUV-induced plasma, for EUV sources up to 250W and beyond. This will combine models and simulations with off-line experiments as well as in-situ scanner tests. It will be shown that our understanding of the underlying mechanisms of plasma-induced release and transport of <1um particles enables us to manage defectivity levels down to be compatible with HVM requirements for sub-10nm node lithography.
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