KEYWORDS: C++, Data modeling, Interfaces, Logic, Field programmable gate arrays, Data storage, Clocks, Signal processing, Signal detection, Optimization (mathematics)
The present paper describes an Electronic System Level (ESL) design methodology which was established and employed
in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description
of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space
exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route
implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time
requirements for QCIF frames.
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