Mr. Mathias Chastan Profile

Mathias Chastan

at STMicroelectronics SA

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Publications (2)

Proceedings Article | 22 February 2021 Poster + Presentation + Paper

Excursion detection and root-cause analysis using virtual overlay metrology

Leon van Dijk, Kedir Adal, Mathias Chastan, Auguste Lam, Richard van Haren

Proceedings Volume 11611, 1161132 (2021) https://doi.org/10.1117/12.2581561

KEYWORDS: Overlay metrology, Data modeling, Semiconducting wafers, Performance modeling, Metrology, Manufacturing, Machine learning, Lithography, Statistical analysis, Scanners

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Overlay is one of the most critical parameters in Integrated Circuit (IC) fabrication as it is a measure for how accurate patterned features are positioned with respect to previously patterned features. Without good overlay, electrical contacts between features will be poor and there can be shorts or opens. Minimizing overlay errors during IC manufacturing is therefore crucial for ensuring high yield and that the performance and reliability specifications of the eventual device are met. For that reason, metrology plays a crucial role in IC fabrication for monitoring the overlay performance and process control. However, due to its high capital equipment cost and impact on cycle time, it is practically impossible to measure every single wafer and/or lot. This means that some excursions cannot be captured and that process drifts might not be detectable in an early phase. Virtual metrology (VM) addresses these challenges as it aims at utilizing the significant amounts of data that are generated during manufacturing by the lithography clusters and other processing equipment, for constructing mathematical and statistical models that predict wafer properties like overlay. In this way, overlay excursions and process drifts can be detected without actually measuring the overlay of these wafers. Preferably, VM is also able to link these excursions and drifts to particular root causes, enabling operators to take preventive measures timely. In this work, we develop virtual overlay metrology for a series of implant layers using a combination of physical and machine learning models. The implant layers relate to ion implantation steps following the Shallow-Trench-Isolation (STI) creation, and both the implant and STI layers are exposed using multiple lithography scanners. A physical model is used to address overlay contributors that can be derived directly from available data. Machine learning algorithms, which are able to learn models from data that can provide predictions for similar, unseen data, are used to predict contributions from less obvious sources of overlay errors. The capability of the overlay prediction model is evaluated on production data. A prediction performance of ~0.7 is achieved in terms of the R-squared statistic and the VM is able to follow variations in the implant-layer overlay and to detect excursions. The excursions can originate from correctable as well as from non-correctable overlay errors. We will show that the interpretability of the prediction model allows us to identify the root cause for the high correctable error variation in the implant-layer overlay. Furthermore, overlay contributors will be identified that may not have a direct impact on the less critical overlay of implant layers. However, they may contribute significantly to the Gate-to-STI overlay as well, and we will show the potential of virtual overlay metrology for downstream layer excursion detection.

Proceedings Article | 22 February 2021 Presentation + Paper

Unsupervised density-based machine learning for abnormal leveling signatures detection

Mathias Chastan, Auguste Lam, Franck Iutzeler

Proceedings Volume 11611, 116111N (2021) https://doi.org/10.1117/12.2581468

KEYWORDS: Semiconducting wafers, Metrology, Zernike polynomials, Process control, Machine learning, Scanners, Wafer-level optics, Sensors, Semiconductor manufacturing, Overlay metrology

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