The pattern size of semiconductor circuits has been shrunk as technical advances continued. Defect control becomes tighter due to a decrease in defect size that affects the image printed on the wafer. It is critical to the photomask which contained a considerably shrunk circuit and ultra-high density pattern for sub – 20 nm tech devices. In this paper we group two types of rare process defects that think come in vacuum chamber contamination here we also present hypothesis defects mechanism and possible solution.
The current Cr etch solutions will need to be improved to keep up with market demand for smaller features and reticle
resolution while the industry awaits the maturity of EUV technology, and based on the current roadmap, there is an urgency
to improve the Cr reticle pattern resolution capability today. That resolution capability comes in the form of writing
smaller features on a photomask, but as the Cr-to-photoresist (PR) ratio increases beyond three to one, there is a negative
impact on the integrity of the PR, resulting in costly product scrap. Thinner PR layers are required to avoid such scrap,
since the Cr layer is fixed. This necessitates lower consumption of the PR during the etch process, and that translates to
higher etch selectivity of Cr to PR. This manuscript covers the ideas selected to address reduction in PR loss, the
experiments around a few of those ideas, and the results of those experiments. Our experimental set shows that a <25%
increase in selectivity and a 40-50% reduction in over-etch can be achieved through increased ion/neutral control during
the etch process. This, combined with resist pretreatments or other Cr etch modifications, could prove to be a solution in
the interim, but while the initial results are promising, further investigation is needed on production nodes to realize the
full impact of this achievement.
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