Mr. Ryuichi Asano Profile

Ryuichi Asano

at Tokyo Electron Ltd.

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Publications (1)

Proceedings Article | 25 May 2022 Presentation + Paper

Nanoimprint edge placement error elements and control

Makoto Ogusu, Masaki Ishida, Masahiro Tamura, Keita Sakai, Toshiki Ito, Yuto Ito, Isao Kawata, Hideki Kunugi, Shuhei Tamura, Ryuichi Asano, Keisuke Tanaka, Tomohito Yamaji

Proceedings Volume 12054, 1205405 (2022) https://doi.org/10.1117/12.2615934

KEYWORDS: Nanoimprint lithography, Etching, Line width roughness, Critical dimension metrology, Overlay metrology

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution. The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices.

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