A new concept of semiconductor lithography is presented. The new technology is tentatively called as New LEEPL since it is an outgrowth of LEEPL which has been developed around 2002. However the new system is completely different from LEEPL. Instead of a single membrane mask used in LEEPL, we use “mask wafer” where mask patterns are made on a wafer by NIL at corresponding positions of chip patterns of chip wafer. The mask patterns on mask wafer have parallel struts structure of 2 division complementary mask (2-DCMPS) Gold (or Si ) dots of thickness of ~50μm are made on the surface of struts and scribing region for equalizing the temperature of mask wafer and chip wafer. Without these contact dots the temperature difference of ~0.5 K will be generated by full power of 1000μA at 2KV. Both mask wafer and chip wafer are cramped together and kept united throughout the processes. The overlay errors between mask patterns and corresponding chip patterns are measured optically. The error map data are fed to 10 e-beam column array to correct the overlay placement errors. Each column does not have main scanning deflector but has tiny deflector only for beam-tilt operation to correct errors. It can deliver 100μA without space charge blur and thus the resolution of L/S pattern of 10nm range can be achieved at resist thickness of 20nm. The e-beam exposure over the mask is performed by the stage motion. Since mask wafer does not have thermal distortion, the thin membrane’s distortion alone will affect the image placement accuracy. In order to obtain less than 1nm distortion of the membrane, the size of 2-DCPS must be smaller 0.7mm.
LEEPL (Low Energy Electron-Beam Proximity Projection Lithography) uses low energy of electrons of 2 KV.
In such a low energy, electrons behaves quite differently in the resist to higher energy electrons even such as in 10
KV. Under these conditions the statistical variations of electrons known as shot noise and its effect to LER is
known to be much smaller than a simple consideration of shot noise variation due to the primary electrons alone.
In order to estimate how much smaller the effective LER in LEEPL, we introduce a reduction factor: f which is the
ratio of the shot noise component of the observed LER against the shot noise factor due to the statistical variation of
primary electrons alone. The value of f was estimated as 0.38 from two independent methods, namely one of from
experimental result and other from the computer simulation. Furthermore the analysis is extended to taking
account of the effect of the acid diffusion in the case of CAR resist. Then the value of f is further reduced to 0.25.
Finally, as consequence of this analysis, we obtain the throughput of LEEPL tool as approximately 80, 60, 40 W/Hr
for 65, 45, 32 nm device nodes respectively. As conclusion, CoO of LEEPL is several times smaller than that of
ArF Immersion and EUV systems.
The concept of LEEPL is based on the discovery that there is a narrow energy space around 2KV of e-beam
proximity lithography where a potential solution for NGL exists. [1]
LEEPL Corporation and LEEPL Technology Consortium consisting of 32 companies have been formed in 2000 and
2001 respectively for the purpose of developing LEEPL technology. The development has been carried out by 1)
building α-tool, 2×β-tools, a pre-production model (LEEPL-3000) and 2) by building the infrastructure supporting
LEEPL technology such as development and supply of LEEPL masks, resist materials, mask inspection and repair tools.
Here LEEPL's overall status and future prospect will be presented for the first time on the base of the past 5
years' intensive effort.
The content of the presentation include LEEPL Development Overview, Exposure and Alignment Systems,
Performance of Resolution, Resist Process, Throughput, and Cost of Ownership Comparison, and LEEPL Mask and
Related Technologies. In conclusion the potential of LEEPL as an alternative solution for future semiconductor
lithography beyond 45 nm node device application will be discussed.
Low energy e-beam proximity projection lithography is proposed for integrated circuit lithography for minimum feature sizes <EQ 0.1 micrometers . This new e-beam lithography is similar to optical projection lithography except that photons are replaced by low energy electrons. The low e-beam energy permits the use of single crystal 0.5 micrometers thick silicon membrane masks without an absorbing metal layer of high atomic number. The membrane mask is thick enough for good heat conduction and thin enough for feature sizes <EQ 0.1 micrometers . The proposed system does not suffer form space charge or proximity effects and is fundamentally a low voltage and low power density lithography with respect to both the mask and the wafer. We predict a throughput of 30 12 inch wafers per hour. Furthermore, the cost of this tool is predicted to be considerably less than today's advanced optical steppers.
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