Dr. Tapan G. Desai Profile

Dr. Tapan G. Desai

at Chemring Sensors & Electronics Systems

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Proceedings Article | 7 March 2014 Paper

Nanoscale coatings for erosion and corrosion protection of copper microchannel coolers for high powered laser diodes

Matthew Flannery, Angie Fan, Tapan Desai

Proceedings Volume 8965, 896505 (2014) https://doi.org/10.1117/12.2037770

KEYWORDS: Corrosion, Copper, Resistance, Gold, Nickel, High power lasers, Diodes, Plating, Semiconductor lasers, Reliability

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High powered laser diodes are used in a wide variety of applications ranging from telecommunications to industrial applications. Copper microchannel coolers (MCCs) utilizing high velocity, de-ionized water coolant are used to maintain diode temperatures in the recommended range to produce stable optical power output and control output wavelength. However, aggressive erosion and corrosion attack from the coolant limits the lifetime of the cooler to only 6 months of operation. Currently, gold plating is the industry standard for corrosion and erosion protection in MCCs. However, this technique cannot perform a pin-hole free coating and furthermore cannot uniformly cover the complex geometries of current MCCs involving small diameter primary and secondary channels. Advanced Cooling Technologies, Inc., presents a corrosion and erosion resistant coating (ANCER^TM) applied by a vapor phase deposition process for enhanced protection of MCCs. To optimize the coating formation and thickness, coated copper samples were tested in 0.125% NaCl solution and high purity de-ionized (DIW) flow loop. The effects of DIW flow rates and qualities on erosion and corrosion of the ANCER^TM coated samples were evaluated in long-term erosion and corrosion testing. The robustness of the coating was also evaluated in thermal cycles between 30°C – 75°C. After 1000 hours flow testing and 30 thermal cycles, the ANCERT^M coated copper MCCs showed a corrosion rate 100 times lower than the gold plated ones and furthermore were barely affected by flow rates or temperatures thus demonstrating superior corrosion and erosion protection and long term reliability.

Proceedings Article | 21 September 2004 Paper

A parallel implementation of LMS adaptive filter in hardware for landmine detection

Tapan Desai, Kenneth Hintz

Proceedings Volume 5415, (2004) https://doi.org/10.1117/12.542097

KEYWORDS: Field programmable gate arrays, General packet radio service, Signal processing, Digital signal processing, Digital filtering, Land mines, Logic, Detection and tracking algorithms, Signal detection, Data acquisition

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Due to the sequential nature of software implementations of the least mean square (LMS) algorithm for processing ground penetrating radar (GPR) signals for landmine detection on uni-processor computers, search area coverage rates are lower than operational needs demand. Since hardware implementations can achieve concurrent execution through parallelization of computational elements, the penalty on execution speed due to sequential execution can be ameliorated. This paper describes a hardware implementation of LMS in a field programmable gate array (FPGA) based on a fully parallel and regular computing architecture. The architecture presented is designed specifically for data collected utilizing the NIITEK Ground Penetrating Radar (GPR), however, due to the regular architecture, this design can be easily modified to suit other sensor data formats. This paper also demonstrates quantitatively the increase in throughput achieved by an implementation on a reconfigurable FPGA compared to the same implementation in sequential software. Finally, we address how reconfigurable hardware can be integrated into an existing detection system. Here, computationally intensive tasks are scheduled to execute on hardware, thereby freeing up a processor to perform other scheduled tasks. This is achieved by embedding field programmable gate array (FPGA) board specific host-to-FPGA application programmer interface (API) calls into an existing software detection system.

Proceedings Article | 11 September 2003 Paper

Volumetric signal processing hardware acceleration for mine detection

Tapan Desai, Kenneth Hintz

Proceedings Volume 5089, (2003) https://doi.org/10.1117/12.487730

KEYWORDS: Field programmable gate arrays, Signal processing, Land mines, Data processing, Clocks, Detection and tracking algorithms, Digital signal processing, Logic, General packet radio service, Optical correlators

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Digital signal processing algorithms for the detection of landmines using ground penetrating radar are computationally intensive if not due to algorithmic complexity, then due to the vast quantity of data which must be processed in real-time. As a result of this, surface area coverage rates using general purpose computers are limited without an additional investment in multiple central processing units and the parallelization of the executable. This results in an excess of unused resources with the associated cost both in terms of monetary cost and power consumption. The increase in power consumption alone also causes an increase cost in cooling and the requirement for larger prime power and/or reduced battery life. Field programmable gate array (FPGA) hardware devices are reconfigurable in seconds and they can be reprogrammed in the field using relatively standard equipment such as a laptop computer. A secondary advantage of re-configurable dedicated hardware is the flexibility it affords in terms of the specific signal processing algorithm being executed on the re-configurable computing device. As an example of this type of hardware optimization of an algorithm, this paper describes an implementation of volumetric (3D) template matching using re-configurable digital hardware, namely an FPGA. This is a viable alternative for the acceleration of digital signal processing and directly results in an increase in mine detection area coverage rates for a relatively small investment. This also results in a more compact, fieldable real-time implementations of landmine detection algorithms and a common mine detector whose hardware is standard but whose optimized algorithms are downloaded into the FPGA for the particular minefield to be cleared. In this paper we give a quantitative analysis of the increase in execution speed achieved by performing cross correlation of large template sizes on large data.

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