KEYWORDS: Etching, System on a chip, Image processing, Sensors, Lithography, Semiconducting wafers, Distance measurement, Process control, Transistors, Signal to noise ratio
BackgroundThe self-aligned double-patterning (SADP) process is being used extensively to overcome the lithographic resolution limit in the manufacture of integrated circuits. One use case is fin definition in a fin field-effect transistor. Fin cut layers are applied to modify the fins to the requirements of the device designs.AimThe traditional secondary electron (SE) imaging exhibits a disadvantage in the process controlling the fin cut layers, and fin damage defects were observed. This work aims to improve the monitoring and controlling capabilities for the process quality of fin cut layers.ApproachA specially designed fin cut process flow and a backscattered electron (BSE) imaging technique are applied to check the process quality. The patterns formed through the fin cut etch and the fin structures are identified and measured simultaneously in one BSE image.ResultsBy measuring the edge-to-edge distance, pitch walking (PW) of fins, and overlay (OV), the root cause of the fin damage is revealed. The linear fitting model and third-order fitting model are applied to reduce the edge placement error (EPE). The edge distance protecting the “at risk” fin is enlarged from 5.6 to 11.6 nm. The range of the distance is reduced from 11.6 to 8.1 nm, and the improvement in standard deviation is about 33%.ConclusionsThis work shows the capability of the BSE imaging technique in the characterization of fin cut layers and the potential in process window improvement restricted to fin damage defects.
This Conference Presentation, “A holistic study of edge placement error on fin cut layer in self-aligned double patterning process,” was recorded at SPIE Photonics West held in San Francisco, California, United States.
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