Microchannel plate is widely used in the field of low light level night vision, photomultiplier, tubes, X-ray enhancer
and so on. In order to meet the requirement of microchannel plate electron multiplier, we used the method of thermal
oxidation to produce a thin film of silicon dioxide which could play a role in electric insulation. Silicon dioxide film
has a high breakdown voltage, it can satisfy the high breakdown voltage requirements of electron multiplier. We
should find the reasonable parameter values and preparation process in the oxidation so that the thickness and
uniformity of the silicon dioxide layer would meet requirement. This article has been focused on researching and
analyzing of the problem of oxide insulation and thermal stress in the process of production of silicon dioxide film.
In this experiment, dry oxygen and wet oxygen were carried out respectively for 8 hours. The thickness of dry
oxygen silicon dioxide films was 458 nm and wet oxygen silicon dioxide films was 1.4 μm. Under these conditions,
the silicon microchannel is uniformity and neat, meanwhile the insulating layer's breakdown voltage was measured
at 450 V after the wet oxygen oxidation. By using ANSYS finite element software, we analyze the thermal stress,
which came from the microchannel oxygen processes, under the conditions of which ambient temperature was 27 ℃
and porosity was 64%, we simulated the thermal stress in the temperature of 1200 ℃ and 1000 ℃, finally we got the
maximum equivalent thermal stress of 472 MPa and 403 MPa respectively. The higher thermal stress area was
spread over Si-SiO2 interface, by simulate conditions 50% porosity silicon microchannel sample was selected for
simulation analysis at 1100 ℃, we got the maximum equivalent thermal stress of 472 MPa, Thermal stress is the
minimum value of 410 MPa.
Anisotropic etching of monocrystalline silicon plays an important role in Microsystems technology in the recent
years. TMAH, as one of the anisotropic etchants, is used to fabricate pores with square cross-section. Careful choice of
concentration, isopropyl alcohol additives and temperature of alkaline solution allows for certain crystallographic
directions to be preferentially etched. In this way, pores with square, eight-sided (octagonal) or rotated square shapes can
be attained and convert to each other. We show the etch selectivity on (100) and (110) planes in TMAH solution with
low concentration. The etch rates on (100) and (110) planes at different temperature and concentration has been
measured. The results indicated that the perfect orthogonal array of pores with sharp edges and corners can be obtained
at more than 40℃ in 1wt% TMAH solution. There is good etch selectivity on (110) surface and the etch rate on (110)
surface is slower than (100) surface under the condition.
The influence of several surfactants in electrolyte during silicon electrochemical etching was reported in this paper. The
morphologies of macroporous silicon arrays in n-type silicon are strongly influenced by the chemical nature of these
additives. Conventional solvents (HF-Ethanol) with cationic (hexadecyl trimethyl ammonium chloride), non-ionic
(Triton-X100) and anionic (sodium alpha-olefin sulfonate) surfactants were experimented respectively. Prominent
differences in microchannel morphologies and apertures were observed depending on the nature of the additive. The
different behaviors of the additives during the electrochemical etching process were linked to the physical properties of
the additives. We found the electric double layer model of the reaction interface partially to explain these results.
However, not only the morphology of the microchannel but also the degree of electrochemical reaction is affected by
surfactant. The anionic surfactant is more suitable for the preparation of silicon microchannel plate with high aspect ratio
and pore size uniform. The depth of microchannels etched by photoelectrochemical etching silicon with anionic
surfactant is 264 μm, and the pore size is 2 μm.
The application fields of high aspect ratio Si microchannel arrays have increased considerably, for example, Si
microchannel plates, MEMS devices and so on. By the method of photo-electrochemical etching (PEC), Si microchannel
arrays are prepared using n-Si wafer covered by anti-corrosion layers and initiation array pits. The dark current intensity
curve of an n-type silicon wafer was presented in aqueous HF. The relationship among temperature, etching voltage and
carrier transportation was presented. The influences of temperature and etching voltage on the surface morphology of
silicon microchannel arrays were researched. The perfect Si microchannel arrays structure with the pore depth of 297 μm,
the pore size of 3 μm and the aspect ratio of 99 was obtained by the method of reducing etching voltage gradually.
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