The benefits of different advanced PVD methods for Ti/TiN films, collimated, longthrow and ionized PVD, are compared to conventional or standard magnetron sputtering with respect to future requirements. Special attention is given to integration aspects in combination with W- plugs and hot Al-fill techniques for contact applications. Besides basic film properties and step coverage data, electrical results for contacts are reported. The dependence of the contact resistance on the bottom Ti thickness is explained, and a new spiking model for Al-filled contacts is proposed. Finally specific manufacturing issues like throughput, target life time and defect densities will be addressed also.

Metal line delay has become increasingly important for ULSI devices. Numerous expressions and software tools have been developed to describe interconnect delay as a function of the geometry and layout. Although many of these formulas have line length effects, this has not been explored in depth. Most software tools are either geared towards circuit designers, or involve more complex and CPU-intensive 3D modeling. In this work, PISCES (a 2D device simulator) was used to extract metal capacitance per unit length. We extend this approach for various lengths by creating a ladder network of the RC components and simulating in SPICE, or using simple closed-form Elmore delay equations. A new key result is that there are optimum metal line width/space for a fixed pitch and height/space ratios that are metal length dependent. For metal lines shorter than about 1500 micrometers , it is better to have narrower metal lines, and for lengths less than 500 micrometers , shrinking metal height is desirable because the penalty in resistance is more than compensated by the decrease in capacitance. For longer lines, the time delay is dominated by resistance, and wider, taller lines are better. Increasing metal spacing or reducing dielectric constant were beneficial for both long and short metal lines.

Characteristics of electroless Cu, Co and Ni alloys for a multilevel metallization as well as for local interconnects and silicide formations for sub-0.5 micrometers ULSIs are presented. An integration of the electroless Cu and CoWP multilayers in an ULSI damascene process for the quarter-micron Cu interconnects of aspect ratio 4:1 is discussed. The following techniques are involved in this process: conformal electroless deposition of CoWP barrier on the thin sputtered Co seed layer, electroless Cu deposition directly onto CoWP barrier to fill a deep trench or a via, removal of the excess barrier and Cu on the oxide by chemical mechanical polishing, Pd activation of the Cu surface and selective electroless CoWP deposition onto Pd- activated in-laid Cu lines to prevent Cu oxidation and corrosion. The study of the selective electroless NiP deposition on Si for silicide formations for sub-0.25micrometers ULSI technology is also presented.

Arcing between the target and plasma during PVD deposition causes substantial damage to the target and splats and other contamination on the deposited films. Arc-related damages and defects are frequently encountered in microelectronics manufacturing and contributes largely to reduced wafer yields. Arcing is caused largely by the charge buildup at the contaminated sites on the target surface that contains either nonconducting inclusions or nodules. Arc suppression is a key issue for defect reduction, yield improvement and for reliable high quality metallization. An Integrated Arc Suppression Unit (IASU) has been designed for Endura HP PVD^TM sputtering sources. The integrated design reduces cable length from unit to source and reduces electrical energy stored in the cable. Active arc handling mode, proactive arc prevention mode, and passive by-pass arc counting mode are incorporated into the same unit. The active mode is designed to quickly respond to chamber conditions, like a large chamber voltage drop, that signals a arc. The self run mode is designed to proactively prevent arc formation by pulsing and reversing target voltage at 50 kHz. The design of the IASU, also called mini small package arc repression circuit--low energy unit (mini Sparc-le), has been optimized for various DC magnetron sources, plasma stability, chamber impedance, power matching, CE MARK test, and power dissipation. Process characterization with Ti, TiN and Al sputtering indicates that the unit has little adverse impact on film properties. Mini Sparc-le unit has been shown here to significantly reduce splats occurrence in Al sputtering. Marathon test of the unit with Ti/TiN test demonstrated the unit's reliability and its ability to reduce sensitivity of defects to target characteristics.

Increasing levels of metallization, shrinking device geometries, and stringent defect density requirements have led to a continuous focus in the semiconductor manufacturing community to reduce defects generated during metal deposition by PVD techniques. Of particular interest in the metallization community is the reduction in in-film defect density in sputtered aluminum films. Pareto analysis of in-film defects in currently used interconnect metallization schemes suggest that a considerable portion of the in-film defects (up to 50%) are caused by unipolar arcing during aluminum deposition. Due to their unusual molten appearance, these defects are commonly referred to as splats. These defects can be as large as 500 micrometers , and due to their frequency of occurrence and size can significantly impact device yield in a manufacturing environment. Systematic investigations have revealed that the formation of splats, due to unipolar arcing, can be strongly correlated to the metallurgy of the aluminum alloy targets used during aluminum sputter deposition. The presence of undesirable metallurgical attributes such as alumina inclusions, porosity, oxygen content etc. are the primary causes for the occurrence of unipolar arcing. These undesirable metallurgical attributes appear to be the result of the manufacturing processes used to manufacture the aluminum alloy targets. The results of this study indicate that significant improvement in defect generation due to unipolar arcing during sputter deposition of aluminum films, and hence an improvement in device yield, is possible by reduction/elimination of the various undesirable metallurgical attributes in the aluminum alloy targets.

Effects of boron and nitrogen on electrical and metallurgical properties of plasma enhanced chemical vapor deposition W-B-N thin film have been investigated. These impurities keep the W-B-N thin film in a nanostructured amorphous phase and provide a stuffing effect that is very effective for preventing the fast diffusion of Cu atoms during a high temperature annealing process. The resistivity of the amorphous W-N and W-B-N thin films is attainable between 140 and 153 (mu) (Omega) -cm by controlling a B₁₀H₁₄/NH₃ flow ratio. XRD, Nomarski microscope, RBS, and TEM analysis show that the W-N and W-B-N barriers do not react with Si during an annealing in Ar ambient at 800 - 900 degree(s)C for 30 min and prevent interdiffusion of the Cu atom at 800 approximately 850 degree(s)C for 30 min, which is the best result regarding to the thermal stability of the diffusion barrier. An electromigration test for a SiO₂/W-N/Al interconnect reveals that a medium time to failure is 2 times that of SiO₂/TiN/Al schemes.

It will be demonstrated that the implementation of chemical mechanical polishing (CMP) for interlayer dielectric (ILD) planarization in a 0.5 micrometers CMOS-technology shows considerable productivity benefits compared to a planarizing resist etchback (PRE) process. Using a BPSG-ILD, the conventional resist etchback ILD-planarization with successive resist spin on and etch back showed high defect densities. These defects are related to the etchback- process. Particles dropping down from the chamber wall onto the wafer act as a mask for the etching process and cause steep, huge defects so called `mesa mountains'. Modifications of the etchback-process reduce the defect density, but there still remains some yield loss. By replacing the PRE sequence with CMP, the measured defect density could be significantly lowered resulting in a considerable yield gain of about 10% relatively. An additional advantage of CMP is the global planarization, which enhances the process window for contact and metal lithography. The smoother topography enables the lithography to reduce the exposure time and, by this, enhances throughput, in addition to the yield gain, a comparison of productivity relevant data show for the ILD-planarization sequence a clear advantage of CMP in cost (-30%) and (-40%).

The chemical mechanical polishing (CMP) of tungsten has been recognized as an enabling technology for sub-half-micron multi-level interconnect. There are many technical challenges to be resolved when incorporating tungsten CMP into the manufacturing line. In this paper, key issues related to the tungsten CMP process--oxide erosion, plug recess, oxide thinning, surface roughness, microscratches, contamination, photolithographic alignment, metal line bridging, via resistance and device yield--were studied for three different types of slurries. The variables studied include pattern density, glue layer thickness, overpolish time and underlying oxide type. Atomic force microscopy, scanning electron microscope and long-scan surface profiler were used. Oxide thinning and erosion were found to depend strongly on slurry type and all the variables studied. With optimized polishing parameters and integration scheme, the tungsten CMP process has enough processing window for manufacturing.

A novel Al-0.5%Cu planarization technology for interconnects is presented using a low pressure Al physical vapor deposition process (or MaxFill^TM), capable of filling high aspect ratio (A/R >= 3) via holes at wafer temperatures of less than or equal to 400 degree(s)C. Excellent Al film reflectivity and surface smoothness are achieved due to hardware modifications to the sputter tool and a modified process flow. A high level of vacuum integrity and cleanliness of the system dramatically reduces the time required to fill 0.35 micrometers via holes with aspect ratios of 3, resulting in a throughput in the excess of 24 wafers per hour. In the present work, a comparison of the film morphology between the traditional Two Step Planarization and MaxFill^TM processes is presented, which shows the improved grain orientation, reflectivity and film roughness of the MaxFill^TM process. The smooth surface morphology of the MaxFill^TM process allows easier alignment during subsequent photolithography. In addition to the film properties, electrical results are presented that show that this new deposition technique can planarize 0.35 micrometers structures with A/R's >= 3 with via resistance values that are lower by a factor of 2.5 than comparable chemically vapor deposited W plug vias.

Ti/TiN liners deposited with Vectra IMP^TM (Ion Metal Plasma) PVD technology can be used as wetting layers to lower the temperature of Al planarization. The Ti/TiN liners can also be used to improve the texture and morphology of the Al overlayer. An experimental investigation was performed to study the impact of the IMP PVD process on the wetting properties of the Ti/TiN films. The Ti/TiN underlayers and the Al overlayer were studied for film morphology and texturing using AFM, XRD, and TEM techniques. It was found that the IMP Ti/TiN process can be used to control and optimize the fill capabilities of low temperature Al planarization. Parameters such as process pressure, bias, process temperature of the IMP Ti and TiN process as well as the wetting layer thickness have significant effects on the grain size, reflectivity, crystal orientation, and surface roughness of the aluminum films. Al films with high reflectivity, low roughness and hyper texturing (< 1 degree(s) FWHM) have been obtained with the integration of IMP Ti/TiN liner module with a low temperature Al planarization module. The fill capability of this integrated process exceeds that of the conventional high temperature Al planarization process at the Via level for a sub 0.25 micrometers IC process.

As devices continuously shrink to deep sub-half micron, the requirements of multilevel interconnect technology become more stringent. A series of device experiments presented here evaluate the integration issues and electrical performance of both logic and SRAM chips fabricated using a low k spin-on material by a non-etchback process. Non-etchback processing is known for it's advantage of reduced cycle time and associated cost saving. Allied Signal's Accuspin 218, a flowable methylsilsesquioxane known for its stable dielectric constant of 2.7, is used throughout the study. Subsequent to SOG coating, several process modifications are implemented to enhance film uniformity and to reduce risks associated with via poisoning. These modifications include a non-conventional two-step baking sequence to enhance film uniformity and a vacuum cure in conjunction with an arsenic implant step to improve via resistance. CMP of the oxide deposited on top of SOG layer is used to provide the required global planarization. CVD tungsten plug process is chosen to test the SOG layer's ability to retain its low dielectric constant after exposure to high temperatures. To insure that photoresist and any polymeric residues are completely removed from the vias, device wafers are subjected to wet stripping and double oxygen plasma ashing. Electrical tests of 0.5 micrometers to 0.35 micrometers vias treated in this manner show that no via poisoning occurs anywhere in the devices. Reliability data from testing of 0.4 micrometers SRAMs is also satisfactory. These results suggest that this low k organic SOG non-etchback process, combined with CMP, is a viable IMD solution for 0.35 micrometers devices.

The HDP-CVD oxide deposition process has been fully investigated with the change of gas flow and RF power up to +/- 20%. The film quality is very stable with a wet etch rate ratio (WERR) of 1.5 relative to thermal oxide. The uniformity for both sputter and deposition are all below 3%, and the D/S ratio is only sensitively affected by bias RF power and side SiH₄ flow. Three important factors, namely bias-RF, backside He flow and O₂/SiH₄ ratio, which affect strongly on the film quality, are studied in detail by measurement of film refractive index, stress, water absorption, WERR, and by pressure cook test (PCT). Lower backside He pressure as well as higher bias-RF power result in higher wafer temperature and better film quality. After PCT, the films do not show any increase in the silanol content and WERR. A liner process with lower bias-RF power is discussed to protect corner sputtering and plasma charging.

Nanoscale oxide thin films such as Ba_1-xSr_xTiO₃ (BST), PbZr_1-xTi_xO₃ (PZT) and SrBi₂(Ta_1-xNb_x)₂O₉ (SBTN) that have high dielectric constant and excellent ferroelectric properties have been receiving greatly increased attention, specially for high density memories in next generation integrated circuits. However, most MOCVD precursors for dielectric and ferroelectric film growth have a very low vaporization pressure and poor thermal stability at elevated temperatures. Moreover, when the film thickness is decreased, the apparent bulk-like properties of thin films tend to worsen due to the increased influence of the interface. In order to solve the problems, novel MOCVD techniques including the development of a new liquid delivery, plasma (ECR or RF) enhanced deposition, TurboDisc technology and two step process were developed. The thickness uniformity, composition uniformity and dielectric and ferroelectric property uniformity of BST, PZT and SBT thin films on 6' Si and Pt wafers are also investigated. Experimental results showed that the new liquid delivery system can improve process reproducibility and increase deposition rates, and the growth reactor with high speed rotation system can deposit homogeneous ultra-thin films on large size substrates, and plasma enhanced MOCVD can reduce the deposition temperature and increase the deposition rate to decrease growth temperature without compromising the quality of the material, and the two step processes can be used to improve interface mismatch between film and substrate. Therefore, high quality dielectric and ferroelectric thin films with nanoscale thickness can be obtained.

During the development of the 0.35 um logic process, a metal side wall undercut has been observed in the post etch cleaning step. The degree of the undercut has been found not only related to the use of the wet chemicals, but also on the layout structure and the subsequent plasma process steps. The sidewall undercut becomes significant if a metal line is in connection to metal pad(s) with adjacent isolated metal lines. It is also noted that if the metal line is in a close loop the side wall is also very susceptible for the damage. Charged induced electrolytic effect and the plasma non-uniformity as well as the local heat dissipation are suspected to be the key factors causing these post etch metal damage. In this paper, we use a specific testing structure with different area ratios to identify these causes and effects. Splits have been done between different wet polymer clean in combination of the plasma photoresist strip process steps. Sheet resistance and cross-sectional pictures are used as the reference to monitor the degree of damage. It was confirmed that though antenna structure is susceptible to this plasma induced electrolytic damage, with a careful selection of the wet chemical polymer clean and resist strip power, the damage can be eliminated.

A Vectra IMP^TM (Ion Metal Plasma) source was used to deposit TiN films for application such as W plug liner and Al wetting layer. The process is based on conventional magnetron sputtering with the addition of a higher density, inductively coupled RF plasma between the sputtering cathode and the substrate. This new technology enables deposition of the films into deep submicron contacts with >50% bottom coverage. In addition to enhancing step coverage of metal films, such as Ti and TiN, this process also has significant effects on the materials properties of the films. The film properties of the TiN films were studied as a function of the fundamental process parameters, namely DC target power, RF coil power, and chamber process pressure, using statistical DOE technique. The study shows that a high degree of control over the film properties can be obtained in the IMP process.

In Intel's manufacturing flow, discrete devices in the scribeline of wafers are tested (E-Test structures) to determine if they meet specifications for reliability and functionality. The wafers are then sorted to determine die functionality. Probing equipment is used to measure E-test structures by way of aluminum pads (E-Test pads) which make contact with devices in the scribeline. Tape automated bonding packaging requires additional processing (compared to Wire Bonded devices) to plate gold bumps on to the die bond pads. The gold bumps are not plated on the E-Test pads but they receive additional processing which may create an insulating surface layer, such as aluminum oxide, preventing the acquisition of reliability information from the wafer tested. If reliability data is not available, wafers are discarded even though the die present on the wafer may be functional. An argon sputter etch procedure is suggested to remove the problematic insulating oxide and recover wafers. The major concerns associated with using a sputter etch recovery procedure include: redistribution of gold across the surface of the wafer; gate charging due to the sputter process; polyimide (PI) surface roughness and thickness issues; encapsulation adhesion issues; and elevated burn-in fallout. This paper will discuss the procedure used to remove surface oxide and experiments to determine if recovery was successful. Process characterization which encompassed etch time and RF power were used to optimize the recovery procedure for reliability purposes. The experimental parameters evaluated include: E-Test parametric data to compare recovered wafers to baseline wafers; threshold voltage data; pad to pad surface leakage due to gold redistribution; SEM cross sections and profilometry to ensure PI integrity; and C-mode Scanning Acoustic Microscopy to address encapsulation adhesion concerns.