Simulation of charging voltages on a wafer during plasma etch

M. Oner; Bharat L. Bhuva; P. Sisterhen; H. Hasan; Sherra E. Kerns

doi:10.1117/12.324389

28 August 1998 Simulation of charging voltages on a wafer during plasma etch

M. Oner, Bharat L. Bhuva, P. Sisterhen, H. Hasan, Sherra E. Kerns

Proceedings Volume 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV; (1998) https://doi.org/10.1117/12.324389
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

During plasma etching, the dependence of gate oxide damage on die location and polarity of the charging voltage will yield devices with varying damage across a wafer. This paper describes a simulator capable of estimating the charging voltage across the gate oxide for any location on a wafer. This tool will enable reliability and process engineers to monitor the damage and identify regions of worst-case damage on a wafer for further testing.

Citation Download Citation

M. Oner, Bharat L. Bhuva, P. Sisterhen, H. Hasan, and Sherra E. Kerns "Simulation of charging voltages on a wafer during plasma etch", Proc. SPIE 3510, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, (28 August 1998); https://doi.org/10.1117/12.324389

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