Methodology for defect impact studies under conditions of low sampling statistics

Andrew Skumanich; Elmira Ryabova

doi:10.1117/12.475646

12 July 2002 Methodology for defect impact studies under conditions of low sampling statistics

Andrew Skumanich, Elmira Ryabova

Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475646
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

A methodology is described which determines the kill rate of defects based on electrical testing using a short loop yield monitoring under conditions of low statistics. The results provide a quantitative means to rank the importance of defects as well as the effectiveness of the inspection strategy. Electrical test results form specifically designed test patterns for interconnect structures and correlated with optical defect inspection data to quantify the kill rates of various defects. A unique and important features of the approach is the use of deliberately introduced defects to study the impact at specific process points. The use of controlled defect inspection at each process step allows an improved statical analysis for low coverage inspection plans. The wafers are optically process step allows an improved statistical analysis for low coverage inspection plans. The wafers are optically inspected at all process steps and reviewed with an automated SEM. The defects are tracked and a defect Pareto is established. The defect management system provides direct correlations between electrical fails and optical defects. It appears that particles that occur at early stages in the process have an enhanced impact because of a potential size amplification effect. With the impact quantified, optimized inspection and defect reduction plans can be implemented.

Citation Download Citation

Andrew Skumanich and Elmira Ryabova "Methodology for defect impact studies under conditions of low sampling statistics", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475646

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