Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um2

Shoji Mimotogi; Fumikatsu Uesawa; Makoto Tominaga; Hiroharu Fujise; Koutaro Sho; Mikio Katsumata; Hiroki Hane; Atsushi Ikegami; Seiji Nagahara; Tatsuhiko Ema; Masafumi Asano; Hideki Kanai; Taiki Kimura; Masaaki Iwai

doi:10.1117/12.711049

27 March 2007 Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um²

Shoji Mimotogi, Fumikatsu Uesawa, Makoto Tominaga, Hiroharu Fujise, Koutaro Sho, Mikio Katsumata, Hiroki Hane, Atsushi Ikegami, Seiji Nagahara, Tatsuhiko Ema, Masafumi Asano, Hideki Kanai, Taiki Kimura, Masaaki Iwai

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Proceedings Volume 6520, Optical Microlithography XX; 652008 (2007) https://doi.org/10.1117/12.711049
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Immersion lithography was applied to 45nm node logic and 0.25um² ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography.

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Shoji Mimotogi, Fumikatsu Uesawa, Makoto Tominaga, Hiroharu Fujise, Koutaro Sho, Mikio Katsumata, Hiroki Hane, Atsushi Ikegami, Seiji Nagahara, Tatsuhiko Ema, Masafumi Asano, Hideki Kanai, Taiki Kimura, and Masaaki Iwai "Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um²", Proc. SPIE 6520, Optical Microlithography XX, 652008 (27 March 2007); https://doi.org/10.1117/12.711049

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