Evaluation of double-patterning techniques for advanced logic nodes

Chiew-Seng Koay; Steven Holmes; Karen Petrillo; Matthew Colburn; Sean Burns; Shannon Dunn; Jason Cantone; David Hetzer; Shinichiro Kawakami; Youri van Dommelen; Aiqin Jiang; Michael Many; Robert Routh; Lior Huli; Brian Martinick; Martin Rodgers; Hideyuki Tomizawa; Sumanth Kini

doi:10.1117/12.846769

3 March 2010 Evaluation of double-patterning techniques for advanced logic nodes

Chiew-Seng Koay, Steven Holmes, Karen Petrillo, Matthew Colburn, Sean Burns, Shannon Dunn, Jason Cantone, David Hetzer, Shinichiro Kawakami, Youri van Dommelen, Aiqin Jiang, Michael Many, Robert Routh, Lior Huli, Brian Martinick, Martin Rodgers, Hideyuki Tomizawa, Sumanth Kini

Author Affiliations +

Proceedings Volume 7640, Optical Microlithography XXIII; 764009 (2010) https://doi.org/10.1117/12.846769
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

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Chiew-Seng Koay, Steven Holmes, Karen Petrillo, Matthew Colburn, Sean Burns, Shannon Dunn, Jason Cantone, David Hetzer, Shinichiro Kawakami, Youri van Dommelen, Aiqin Jiang, Michael Many, Robert Routh, Lior Huli, Brian Martinick, Martin Rodgers, Hideyuki Tomizawa, and Sumanth Kini "Evaluation of double-patterning techniques for advanced logic nodes", Proc. SPIE 7640, Optical Microlithography XXIII, 764009 (3 March 2010); https://doi.org/10.1117/12.846769

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