Full-chip correction of implant layer accounting for underlying topography

Minchul Oh; Hyungjoo Youn; Noyoung Chung; Jaeyeol Maeng; Sukjoo Lee; Jahum Ku; Aasutosh Dave; John L. Sturtevant; Uwe Hollerbach; Thuy Do; Yuri Granik; Kostas Adam; Juhwan Kim; Cynthia Zhu; S. W. Jung

doi:10.1117/12.917984

13 March 2012 Full-chip correction of implant layer accounting for underlying topography

Minchul Oh, Hyungjoo Youn, Noyoung Chung, Jaeyeol Maeng, Sukjoo Lee, Jahum Ku, Aasutosh Dave, John L. Sturtevant, Uwe Hollerbach, Thuy Do, Yuri Granik, Kostas Adam, Juhwan Kim, Cynthia Zhu, S. W. Jung

Author Affiliations +

Proceedings Volume 8326, Optical Microlithography XXV; 83262R (2012) https://doi.org/10.1117/12.917984
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge placement control budgets for junction definition shrink with each node. In addition to the traditional proximity effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls, reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an optical model representing only implant mask proximity effects and two additional optical models which represent the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD control for complex layouts, and represents only a small impact to full-chip correction runtime.

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Minchul Oh, Hyungjoo Youn, Noyoung Chung, Jaeyeol Maeng, Sukjoo Lee, Jahum Ku, Aasutosh Dave, John L. Sturtevant, Uwe Hollerbach, Thuy Do, Yuri Granik, Kostas Adam, Juhwan Kim, Cynthia Zhu, and S. W. Jung "Full-chip correction of implant layer accounting for underlying topography", Proc. SPIE 8326, Optical Microlithography XXV, 83262R (13 March 2012); https://doi.org/10.1117/12.917984

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