Paper
22 August 2014 Clock and carrier recovery in high-speed coherent optical communication systems
Author Affiliations +
Proceedings Volume 9286, Second International Conference on Applications of Optics and Photonics; 92864M (2014) https://doi.org/10.1117/12.2063761
Event: Second International Conference on Applications of Optics and Photonics, 2014, Aveiro, Portugal
Abstract
In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Sofia B. Amado, Ricardo Ferreira, Pedro S. Costa, Fernando P. Guiomar, Somayeh Ziaie, António L. Teixeira, Nelson J. Muga, and Armando N. Pinto "Clock and carrier recovery in high-speed coherent optical communication systems", Proc. SPIE 9286, Second International Conference on Applications of Optics and Photonics, 92864M (22 August 2014); https://doi.org/10.1117/12.2063761
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Cited by 2 scholarly publications.
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KEYWORDS
Clocks

Error analysis

Digital signal processing

Phase shift keying

Field programmable gate arrays

Receivers

Statistical analysis

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