Interests: Technologies, products, and applications for efficient manufacture of thin film electronic devices, integrated optics and similar structures.
Managed Intel’s first Proteus OPC technology transfer to shrink. Executed model based design validation and process margin improvements, meeting yield objectives on the 1st lot out. Enabled accelerated new technology qualification and conversion to shrink of all LOGIC products.
Investigated manufacturability of optical resolution enhancements for applications in microlithography. Invented and implemented effective 2-D OPC using optimal e-test based serif design, automated full-chip insertion and design validation. Extended lithography process window and yield from k1=1.0 to 0.5. Spearheaded industry-wide lithography extensions with OPC enabled by CAD/EDA, mask making, inspection and dimensional metrology.
Developed alignment and overlay metrology at IBM. Troubleshot alignment issues with Censor and GCA, collaborated on alignment in step-and-scan JD with Perkin-Elmer. Characterized and modeled error mechanisms, established effective performance metrics (now standard), enabled and drove improvements, influenced equipment vendors, consortia and industry. According to VLSI Research, “forever changed overlay measurement requirements”.
Lead metrology-process integration in IBM-Siemens-Toshiba DRAM partnerships resulting in elimination of a widely anticipated overlay roadblock at 250nm/256Mb. Co-developed SEM based in-die overlay metrology for FE and AlCu/W Damascene BE. Invented effective dose and focus monitors for applications with optical metrology tools.
Managed Ultratech Alignment/Metrology Engineering, supported applications, collaborated with strategic customers. Delivered wafer global and fine alignment in narrow scribes. Developed stepper self-metrology and accelerated reduction of alignment and registration error, improved tool stability and matching. Enabled new market penetration and new system sales
Managed Intel’s first Proteus OPC technology transfer to shrink. Executed model based design validation and process margin improvements, meeting yield objectives on the 1st lot out. Enabled accelerated new technology qualification and conversion to shrink of all LOGIC products.
Investigated manufacturability of optical resolution enhancements for applications in microlithography. Invented and implemented effective 2-D OPC using optimal e-test based serif design, automated full-chip insertion and design validation. Extended lithography process window and yield from k1=1.0 to 0.5. Spearheaded industry-wide lithography extensions with OPC enabled by CAD/EDA, mask making, inspection and dimensional metrology.
Developed alignment and overlay metrology at IBM. Troubleshot alignment issues with Censor and GCA, collaborated on alignment in step-and-scan JD with Perkin-Elmer. Characterized and modeled error mechanisms, established effective performance metrics (now standard), enabled and drove improvements, influenced equipment vendors, consortia and industry. According to VLSI Research, “forever changed overlay measurement requirements”.
Lead metrology-process integration in IBM-Siemens-Toshiba DRAM partnerships resulting in elimination of a widely anticipated overlay roadblock at 250nm/256Mb. Co-developed SEM based in-die overlay metrology for FE and AlCu/W Damascene BE. Invented effective dose and focus monitors for applications with optical metrology tools.
Managed Ultratech Alignment/Metrology Engineering, supported applications, collaborated with strategic customers. Delivered wafer global and fine alignment in narrow scribes. Developed stepper self-metrology and accelerated reduction of alignment and registration error, improved tool stability and matching. Enabled new market penetration and new system sales
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