Dr. Anand Gupta Profile

Dr. Anand Gupta

at Real Time Metrology Inc

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Proceedings Article | 25 March 2008 Paper

High throughput wafer defect monitor for integrated metrology applications in photolithography

Nagaraja Rao, Patrick Kinney, Anand Gupta

Proceedings Volume 6922, 69223B (2008) https://doi.org/10.1117/12.772384

KEYWORDS: Semiconducting wafers, Particles, Nanoimprint lithography, Inspection, Image filtering, Silicon, Wafer inspection, Wafer testing, Metrology, Image processing

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The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Proceedings Article | 4 September 1998 Paper

Copper post-CMP cleaning process on a dry-in/dry-out tool

Sanjay Basak, Malcolm Grief, Anand Gupta, Krishna Murella, Barrie VanDevender

Proceedings Volume 3508, (1998) https://doi.org/10.1117/12.324033

KEYWORDS: Copper, Semiconducting wafers, Chemical mechanical planarization, Polishing, Particles, Chemistry, Oxides, Metals, Semiconductor manufacturing, Surface finishing

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Metal Chemical Mechanical Planarization (CMP) and post CMP cleaning have continued to increase in importance in semiconductor manufacturing. The introduction of copper metallization into semiconductor manufacturing processes has created a need for integrating CMP and cleaning tools, as well as a demand for the development of novel cleaning solutions. One system designed for integrated CMP processing and cleaning, commonly referred to as dry-in/dry-out CMP, is the SpeedFam Auriga C. The Auriga C integrates a widely used polishing tool together with a proven cleaning technique. The key to the operation of the Auriga C cleaning process is the effective operation of the PVA brush cleaners, water track transport, final jet rinse and high-speed spinner dryer. The effective operation of the cleaning mechanism for copper post- CMP cleaning requires the use of new chemical solutions. Typical solutions used for post process cleaning of more mature CMP processes are either ineffective for cleaning or chemically incompatible with the copper process. This paper discusses the cleaning mechanism used in an integrated dry- in/dry-out tool and demonstrates an effective and novel cleaning solution for use with this type of post-CMP cleaning process.

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