KEYWORDS: Etching, System on a chip, Plasma, Lithography, Semiconducting wafers, Photoresist materials, 3D modeling, Back end of line, Numerical simulations
A double patterning Litho-Etch-Litho-Etch (LELE) process developed in a test vehicle for Back End of Line manufacturing is investigated using rigorous, physics-based three-dimensional computational models. The wafer topography consists of TiN, SiO2, Spin-on-Carbon, Spin-on-Glass (SOG), over which the photoresist patterns are printed. The lithography step of the LELE flow is simulated using PROLITH, and the etching steps are simulated using ProETCH, a new dry etch simulator developed at KLA. Two clips that are spatially close to another and present in the photomask layout for the first and second lithography steps are considered to investigate the impact of etch process conditions on etch bias. We found that the final etch bias during the LELE processes is dominantly induced during the etch of SOG. The tapered profiles induced during the SOG etch process are due to the polymerization by CFx radicals produced in the plasma. The effect of varying the neutral-ion-flux ratio on the etch bias is investigated. Etch process development for SOG needs to balance multiple targets to avoid defect formation.
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