KEYWORDS: Overlay metrology, Image segmentation, Scatterometry, Metrology, Semiconducting wafers, Front end of line, Back end of line, Optical lithography, Inspection, Optical filters, Sensors, Reflectivity, Solids
Having a well designed overlay metrology target is one of the ways to improve on-product overlay performance. The traditional screening method in which multiple targets types are added to successive reticle tape outs and then evaluated by trial-and-error may not suffice for the 7nm node and beyond. For instance, although segmentation of image-based overlay target has been reported by many as a means for improving overlay measurement, we find that segmentation does not guarantee improvement. In fact it can be undesirable. Fundamental understandings of metrology and wafer process are required to properly design the targets and carefully optimize them for a given process stack involving multilevel measurement. This paper investigates the Blossom, AIM, and scatterometry targets at the FEOL, MOL, and BEOL patterning levels in 7nm node to gain knowledge needed in order to comprehensively map out the overlay target solutions for future nodes.
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