Yield forecasting is a key component in running a successful semiconductor fab. It is also a significant challenge for facilities such as ASIC houses, which fabricate a wide range of devices using multiple technologies. Yield forecasting takes on increased significance in these environments, with new products introduced frequently and many products running only in small numbers. An accurate yield prediction system can greatly accelerate the process of identifying design bugs, test program issues and process integration problems. To this end, we have constructed a forecasting model geared for our ASIC manufacturing line. The model will accommodate an arbitrary number of design and/or process elements, each with an associated defectivity term. In addition, we have automated the generation of the yield forecast through passively linking to the already existing EDA design tools and scripts used by LSI Logic. Once the model is constructed, an automated query engine can extract the design and process parameters for any requested device, insert the data into the forecasting model, and deliver the resulting yield prediction. The actual yield for any lot or group of lots may thus be compared to the forecast, greatly assisting yield enhancement activities. This is especially useful for prototype lots and low-volume devices, for which it eliminates a great deal of manual computation and searching of design files. Using the model in conjunction with the query engine, any deviations from expected yield performance are generated automatically, quickly and efficiently highlighting opportunities for improvement.
High-speed production of semiconductor devices demands in-line wafer metrology on a minimum number of sample points. If this data does not represent the average chip feature size, then an in-line monitor may indicate that a wafer is right on target. However, at end-of-line testing, the electrical parameters, incorporating all features within the chip, may be found shifted away from target. This paper presents a solution which increases wafer critical dimension targeting efficiency while notably relaxing the traditional mean-to-target reticle specification. By embedding ART (Average Representative Targeting) Structures into the reticle scribe, Reticle Engineering at LSI Logic leverage off the ability to adjust wafer exposure dose to compensate for off target reticle CDs. The novel targeting structure described in this paper assures average wafer CDs within 2.5 nm of target while effectively doubling the acceptable range for a standard mean to target reticle specification.
Broadly tunable solid state lasers in the near infrared can be created using Cr4+ ions doped in various host lattices. Cr:forsterite and Cr:YAG span much of the spectral region between 1.2 and 1.56 micrometers . New hosts are required for powerful operation at 1.32 micrometers . Novel laser structures may be possible using optical nanocrystals embedded in refractive-index matched hosts. Waveguides with net gain are possible using Cr-doped nanocrystals.
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