Mr. Frank Hsieh Profile

Frank Hsieh

Section Manager at Toppan Chunghwa Electronics Co Ltd

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Publications (7)

Proceedings Article | 20 August 2004 Paper

Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL

Michael Hsu, Thomas Laidig, Kurt Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke, Frank Hsieh

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557792

KEYWORDS: Photomasks, Manufacturing, Optical proximity correction, Semiconducting wafers, Printing, Critical dimension metrology, Computer aided design, Reliability, Mask making, Resolution enhancement technologies

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Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

Proceedings Article | 20 August 2004 Paper

Evaluation, reduction, and monitoring of progressive defects on 193-nm reticles for low-k1 process

Chia Hwa Shiao, Chien-Chung Tsai, Tony Hsu, Steve Tuan, Doris Chang, Richard Chen, Frank Hsieh

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557702

KEYWORDS: Photomasks, Contamination, Pellicles, Reticles, Air contamination, Semiconducting wafers, Inspection, 193nm lithography, Manufacturing, Control systems

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Proceedings Article | 17 December 2003 Paper

Implementing AAPSM in 90-nm product with practical image imbalance correction

Benjamin Lin, Shu-hao Hsu, I. H. Huang, Kunyuan Chen, Frank Hsieh, Tony Hsu, Hua-Yu Liu, Armen Kroyan, Freeman Hsu, Jason Huang

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518029

KEYWORDS: Photomasks, Semiconducting wafers, Quartz, Optical proximity correction, Binary data, Phase shifts, Reticles, Neodymium, Optical lithography, Manufacturing

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Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.

Proceedings Article | 28 August 2003 Paper

Low k1 lithography patterning option for the 90-nm and 65-nm nodes

Stephen Hsu, Douglas Van Den Broeke, Xuelong Shi, Michael Hsu, Kurt Wampler, J. Fung Chen, Annie Yu, Samuel Yang, Frank Hsieh

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504394

KEYWORDS: Photomasks, Reticles, Manufacturing, Phase shifts, Lithography, Nanoimprint lithography, Etching, Quartz, Image transmission, Transmittance

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Proceedings Article | 28 August 2003 Paper

Practical approach for AAPSM image imbalance correction for sub-100-nm lithography

Hung Lin Cho, Shu Yi Lin, Frank Hsieh, Armen Kroyan, Hua-Yu Liu, Jason Huang, Shu-Hao Hsu, I-Hsiung Huang, Benjamin Lin, Kuei-Chun Hung

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504393

KEYWORDS: Photomasks, Chromium, Critical dimension metrology, Manufacturing, Lithography, Semiconducting wafers, Reticles, Scanning electron microscopy, Optical proximity correction, Image resolution

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Proceedings Article | 28 August 2003 Paper

Investigation of phase variation impact on CPL PSM for low k1 imaging

Chun-hung Lin, Michael Hsu, Frank Hsieh, Shu Yi Lin, Stephen Hsu, Xuelong Shi, Douglas Van Den Broeke, J. Fung Chen, F. Tang, W. Hsieh, C. Huang

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504176

KEYWORDS: Etching, Photomasks, Critical dimension metrology, Semiconducting wafers, Quartz, Printing, Image processing, Metrology, Process control, Phase shifting

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Proceedings Article | 26 June 2003 Paper

65-nm full-chip implementation using double dipole lithography

Stephen Hsu, J. Fung Chen, Noel Cororan, William Knose, Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Xuelong Shi, Michael Hsu, Mark Eurlings, Jo Finders, Tsann-Bim Chiou, Robert Socha, Will Conley, Yen Hsieh, Steve Tuan, Frank Hsieh

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485445

KEYWORDS: Reticles, Photomasks, Model-based design, Scattering, Optical proximity correction, Stray light, Resolution enhancement technologies, 3D modeling, Logic, Binary data

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Showing 5 of 7 publications

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