Dr. Robert J. Socha Profile

Dr. Robert J. Socha

Imaging Scientist at ASML US Inc

SPIE Involvement:

Author | Instructor

Publications (105)

Proceedings Article | 25 March 2020 Paper

Holistic method for reducing overlay error at the 5nm node and beyond

Robert Socha

Proceedings Volume 11328, 113280V (2020) https://doi.org/10.1117/12.2554799

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Proceedings Article | 20 March 2019 Paper

Holistic feedforward control for the 5 nm logic node and beyond

Henry Megens, Ralph Brinkhof, Igor Aarts, Haico Kok, Leendertjan Karssemeijer, Gijs ten Haaf, Shawn Lee, Daan Slotboom, Chris de Ruiter, Irina Lyulina, Simon Huisman, Stefan Keij, Evert Mos, Wim Tel, Manouk Rijpstra, Emil Schmitt-Weaver, Kaustuve Bhattacharyya, Robert Socha, Boris Menchtchikov, Michael Kubis, Jan Mulkens

Proceedings Volume 10961, 109610K (2019) https://doi.org/10.1117/12.2515449

KEYWORDS: Lithographic process control, Semiconducting wafers, Optical alignment, Overlay metrology, Sensors, Distortion, Scanners, Logic, Metrology, Process control

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Proceedings Article | 20 March 2018 Paper

Reduction in overlay error from mark asymmetry using simulation, ORION, and alignment models

Boris Menchtchikov, Robert Socha, Chumeng Zheng, Sudhar Raghunathan, Igor Aarts, Krishanu Shome, Jonathan Lee, Chris de Ruiter, Manouk Rijpstra, Henry Megens, Ralph Brinkhof, Floris Teeuwisse, Leendertjan Karssemeijer, Irina Lyulina, Chung-Tien Li, Jan Hermans, Philippe Leray

Proceedings Volume 10587, 105870C (2018) https://doi.org/10.1117/12.2297493

KEYWORDS: Optical alignment, Monte Carlo methods, Overlay metrology, Polarization, Sensors, Chemical mechanical planarization, Etching, Scanners

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Proceedings Article | 30 March 2017 Paper

Computational scanner wafer mark alignment

Boris Menchtchikov, Robert Socha, Sudharshanan Raghunathan, Irina Lyulina, Hielke Schoonewelle, Patrick Tinnemans, Paul Tuffy, Philippe Leray, Christiane Jehoul

Proceedings Volume 10147, 101471C (2017) https://doi.org/10.1117/12.2259750

KEYWORDS: Far infrared, Optical alignment, Semiconducting wafers, Sensors, Signal detection, Avalanche photodetectors, Signal processing, Scanners, Optical lithography, Overlay metrology

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Proceedings Article | 24 March 2017 Paper

Impact of EUV SRAF on Bossung tilt

Yow-Gwo Wang, Stephen Hsu, Robert Socha, Andy Neureuther, Patrick Naulleau

Proceedings Volume 10143, 1014320 (2017) https://doi.org/10.1117/12.2260160

KEYWORDS: SRAF, Photomasks, Extreme ultraviolet lithography, 3D image processing, Diffraction, 3D modeling, Zernike polynomials, Imaging systems, Image processing, Lithographic illumination, Critical dimension metrology

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Proceedings Article | 24 March 2016 Paper

Improving scanner wafer alignment performance by target optimization

Philippe Leray, Christiane Jehoul, Robert Socha, Boris Menchtchikov, Sudhar Raghunathan, Eric Kent, Hielke Schoonewelle, Patrick Tinnemans, Paul Tuffy, Jun Belen, Rich Wise

Proceedings Volume 9778, 97782M (2016) https://doi.org/10.1117/12.2219491

KEYWORDS: Optical alignment, Semiconducting wafers, Overlay metrology, Scanners, Etching, Avalanche photodetectors, Optical lithography, Silicon, Metrology, Chemical mechanical planarization

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Proceedings Article | 23 March 2011 Paper

Improved fab CDU with FlexRay and LithoTuner

Robert Socha, Wenjin Shao, Xu Xie, Youri van Dommelen, Dorothe Oorschot, Henry Megens, Venu Vellanki

Proceedings Volume 7973, 79730Q (2011) https://doi.org/10.1117/12.879619

KEYWORDS: Scanners, Critical dimension metrology, Semiconducting wafers, Data modeling, Diffractive optical elements, Calibration, Optical proximity correction, Micromirrors, Metrology, Lithography

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Proceedings Article | 23 March 2011 Paper

Freeform and SMO

Robert Socha

Proceedings Volume 7973, 797305 (2011) https://doi.org/10.1117/12.883317

KEYWORDS: Polarization, Diffraction, Source mask optimization, Electroluminescence, Photomasks, Photoresist materials, Semiconducting wafers, Thin films, Fiber optic illuminators, Scanners

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SPIE Journal Paper | 1 January 2011

Experimental verification of source-mask optimization and freeform illumination for 22-nm node static random access memory cells

Joost Bekaert, Bart Laenens, Staf Verhaegen, Lieve Van Look, Darko Trivkovic, Frederic Lazzarino, Geert Vandenberghe, Paul van Adrichem, Robert Socha, Stephen Hsu, Hua-yu Liu, Orion Mouraille, Koen Schreel, Mircea Dusa, Jörg Zimmermann, Paul Gräupner, Jens Neumann

JM3, Vol. 10, Issue 1, 013008, (January 2011) https://doi.org/10.1117/12.10.1117/1.3541778

KEYWORDS: Source mask optimization, Photomasks, Diffractive optical elements, Semiconducting wafers, Scanners, Manufacturing, Double patterning technology, Fiber optic illuminators, Optical lithography, Lithographic illumination

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Proceedings Article | 8 June 2010 Paper

Design compliant source mask optimization (SMO)

Robert Socha, Tejas Jhaveri, Mircea Dusa, Xiaofeng Liu, Luoqi Chen, Stephen Hsu, Zhipan Li, Andrzej Strojwas

Proceedings Volume 7748, 77480T (2010) https://doi.org/10.1117/12.865781

KEYWORDS: Source mask optimization, Photomasks, Photovoltaics, Logic, Feedback loops, Lithography, Metals, Electroluminescence, Diffractive optical elements, Manufacturing

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Proceedings Article | 4 March 2010 Paper

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

J. Bekaert, B. Laenens, S. Verhaegen, L. Van Look, D. Trivkovic, F. Lazzarino, G. Vandenberghe, P. van Adrichem, R. Socha, S. Baron, M. C. Tsai, K. Ning, S. Hsu, H. Y. Liu, M. Mulder, A. Bouma, E. van der Heijden, O. Mouraille, K. Schreel, J. Finders, M. Dusa, J. Zimmermann, P. Gräupner, J. T. Neumann, C. Hennerkes

Proceedings Volume 7640, 764008 (2010) https://doi.org/10.1117/12.846918

KEYWORDS: Source mask optimization, Photomasks, Semiconducting wafers, Diffractive optical elements, Manufacturing, Double patterning technology, Scanners, Electroluminescence, Fiber optic illuminators, Optical lithography

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Proceedings Article | 4 March 2010 Paper

Performance of FlexRay: a fully programmable illumination system for generation of freeform sources on high NA immersion systems

Melchior Mulder, André Engelen, Oscar Noordman, Gert Streutker, Bert van Drieenhuizen, Cas van Nuenen, Wilfred Endendijk, Jef Verbeeck, Wim Bouman, Anita Bouma, Robert Kazinczi, Robert Socha, Dirk Jürgens, Joerg Zimmermann, Bastian Trauter, Joost Bekaert, Bart Laenens, Daniel Corliss, Greg McIntyre

Proceedings Volume 7640, 76401P (2010) https://doi.org/10.1117/12.845984

KEYWORDS: Mirrors, Diffractive optical elements, Fiber optic illuminators, Source mask optimization, Imaging systems, Electroluminescence, Polarization, Semiconducting wafers, Photomasks, Light

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Proceedings Article | 4 March 2010 Paper

22nm logic lithography in the presence of local interconnect

Michael Smayling, Robert Socha, Mircea Dusa

Proceedings Volume 7640, 764019 (2010) https://doi.org/10.1117/12.846580

KEYWORDS: Photomasks, Metals, Lithography, Optical lithography, Logic, Source mask optimization, Photovoltaics, Optical proximity correction, Lithium, SRAF

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The 22nm logic node is being approached from at least two different scaling paths. One approach "B" will use Gate and 1x Metal pitches of approximately 80nm, which, combined with the appropriate design style, may allow single exposure to be used. The other combination under consideration "A" will have a Gate pitch of ~90nm and a 1x Metal pitch of 70nm. Even with immersion scanners, the Rayleigh k1 factor is below 0.32 for 90nm pitch and below the single exposure resolution limits when the pitch is below 80nm. Although highly regular gridded patterns help [1,2,3], one of the critical issues for 22nm patterning is Contact and Via patterning. The lines / cuts approach works well for the poly and interconnect layers, but the "hole" layers have less benefit from gridded designs and remain a big challenge for patterning. One approach to reduce the lithography optimization problem is to reconsider the interconnection stack. The Contact layer is complex because it is connecting two layers on the bottom - Active and Gate - to one layer on the top. Other layers such as Via-1 only have one layer on the bottom. A potential solution is a Local Interconnect layer. This layer could be formed as part of the salicide process module, where a patterned etch would replace the blanket strip of un-reacted metal of the silicide layer. Local interconnect lines would run parallel to the Gate electrodes, eliminating "wrong-way" lines in the Active layer. Depending on the final pitch chosen, Local Interconnect could be single or double patterned, or could be done with a self-aligned process plus a cut mask. Example layouts of standard cells have shown a significant benefit with local interconnects. For example, the Contact count is reduced by ~25%, and in many cases Via-1 and Metal-2 usage was eliminated. The simplified Active pattern, along with reduced contact count and density, permit a different lithography optimization for the cells designed with Local Interconnect. Metal-1 complexity was also reduced. Details of lithography optimization results for critical layers, Active, Gate, Local Interconnect, Contact, and Metal-1 will be presented.

Proceedings Article | 10 December 2009 Paper

Source-mask co-optimization: optimize design for imaging and impact of source complexity on lithography performance

Stephen Hsu, Zhipan Li, Luoqi Chen, Keith Gronlund, Hua-yu Liu, Robert Socha

Proceedings Volume 7520, 75200D (2009) https://doi.org/10.1117/12.838701

KEYWORDS: Source mask optimization, Lithography, Photomasks, Diffractive optical elements, Photovoltaics, Atrial fibrillation, Optimization (mathematics), Electroluminescence, Optical lithography, Extreme ultraviolet lithography

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Proceedings Article | 6 March 2009 Paper

Improved model predictability by machine data in computational lithography and application to laser bandwidth tuning

Stefan Hunsche, Qian Zhao, Xu Xie, Robert Socha, Hua-Yu Liu, Peter Nikolsky, Anthony Ngai, Paul van Adrichem, Michael Crouse, Ivan Lalovic

Proceedings Volume 7274, 727405 (2009) https://doi.org/10.1117/12.814644

KEYWORDS: Data modeling, Scanners, Semiconducting wafers, Calibration, Process modeling, Fiber optic illuminators, Model-based design, Optical proximity correction, Photomasks, Computational lithography

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Proceedings Article | 4 December 2008 Paper

Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies

Tsann-Bim Chiou, Robert Socha, Ho-Young Kang, Alek Chen, Stephen Hsu, Hong Chen, Luoqi Chen

Proceedings Volume 7140, 71401Z (2008) https://doi.org/10.1117/12.804763

KEYWORDS: Model-based design, Photomasks, Optical proximity correction, Lithography, Design for manufacturing, Double patterning technology, Imaging systems, Logic, Scanners, Extreme ultraviolet lithography

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When k1 is smaller than the resolution limit, e.g., for a half-pitch (HP) ≤32nm, the most advanced immersion scanner does not have sufficient imaging capability. Extreme ultraviolet (EUV) technology at wavelength of 13.5nm is considered a practical light source for next-generation lithographic technology [1,2]. However, before EUV lithography is suited to mass production, an appropriate exposure technology is needed to fill the gap between immersion ArF and EUV scanners. Double patterning technology (DPT) is a technology that extends the usability of immersion ArF systems. Notably, DPT relaxes the minimum pitch of a circuit layout for each split exposure; thus, ArF water-based immersion systems can be extended to 32 nm node and beyond. Improvements to exposure system hardware are needed to enhance imaging, overlay, and productivity performance. Additionally, patterning-related processes [3-5] must be improved to ensure patterning fidelity when two splits are combined. The remaining challenge is to develop an intelligent approach for splitting the original layout to two different exposure mask layouts. Generally, DPT can be categorized as two types according to its applications. One type is the so-called 'litho DPT,' which adopts dual litho-etching steps. The final pattern is a combination of two individual litho-etched patterns. In this case, a normal pattern-splitting method is required to keep the minimum HP of separate patterns as large as possible. The best method for pattern splitting is to use a rule-based approach, which separates features according to their geometrical information such as edge-to-edge and/or vertex-to-vertex distance. When using a rule-based scheme, a full-chip pattern decomposition is practical because it can has fast processing speed. The other type is 'spacer DPT,' which adopts a single split pattern as a sacrificial layer to form spacers deposited onto pattern edges. The idea implies that one can arbitrarily select one of the split layouts. However, a normal pattern-splitting technique is still required. With the assistance of polygon Boolean operations, the trim layout (to remove residual polygons) and makeup layout (to repair irregular missing polygons) can be generated using scripting electronic design automation (EDA) software. In this study, some examples of pattern splitting are demonstrated using the Tachyon pattern-splitting tool. Furthermore, Tachyon scripts are utilized to create layouts with consideration of OPC for spacer DPT. The patterns created after each process step can be emulated with the scripts to help the process verification. All techniques developed in this study for DPT pattern splitting are applicable for 32nm node and beyond.

Proceedings Article | 4 December 2008 Paper

An innovative Source-Mask co-Optimization (SMO) method for extending low k1 imaging

Stephen Hsu, Luoqi Chen, Zhipan Li, Sean Park, Keith Gronlund, Hua-Yu Liu, Neal Callan, Robert Socha, Steve Hansen

Proceedings Volume 7140, 714010 (2008) https://doi.org/10.1117/12.806657

KEYWORDS: Diffractive optical elements, Photomasks, Source mask optimization, Atrial fibrillation, Optical proximity correction, Fiber optic illuminators, Nanoimprint lithography, Scanners, Electroluminescence, Lithography

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Proceedings Article | 19 May 2008 Paper

Separable OPC models for computational lithography

Hua-Yu Liu, Qian Zhao, J. Fung Chen, Jiong Jiang, Robert Socha, Eelco Van Setten, Andre Engelen, Jeroen Meessen, Michael Crouse, Mu Feng, Wenjin Shao, Hua Cao, Yu Cao, Lieve Van Look, Joost Bekaert, Geert Vandenberghe, Jo Finders

Proceedings Volume 7028, 70280X (2008) https://doi.org/10.1117/12.793039

KEYWORDS: 3D modeling, Optical proximity correction, Calibration, Photomasks, Data modeling, Semiconducting wafers, Performance modeling, Finite element methods, Lithography, Wafer-level optics

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Proceedings Article | 12 March 2008 Paper

Understanding illumination effects for control of optical proximity effects (OPE)

Donis Flagello, Bernd Geh, Robert Socha, Peng Liu, Yu Cao, Roland Stas, Oliver Natt, Jörg Zimmermann

Proceedings Volume 6924, 69241U (2008) https://doi.org/10.1117/12.773632

KEYWORDS: Modulation transfer functions, Fiber optic illuminators, Optical proximity correction, Data modeling, Critical dimension metrology, Lenses, Photomasks, Optical transfer functions, Scanning laser ophthalmoscopy, Laser imaging

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Proceedings Article | 12 March 2008 Paper

Development of a computational lithography roadmap

J. Fung Chen, Hua-Yu Liu, Thomas Laidig, Christian Zuniga, Yu Cao, Robert Socha

Proceedings Volume 6924, 69241C (2008) https://doi.org/10.1117/12.773060

KEYWORDS: Optical proximity correction, Extreme ultraviolet, Computational lithography, Photomasks, Lithography, Calibration, Extreme ultraviolet lithography, Manufacturing, Resolution enhancement technologies, Polarization

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Proceedings Article | 7 March 2008 Paper

Development of layout split algorithms and printability evaluation for double patterning technology

Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten, Alek Chen

Proceedings Volume 6924, 69243M (2008) https://doi.org/10.1117/12.773107

KEYWORDS: Model-based design, Optical proximity correction, Algorithm development, Design for manufacturing, Photomasks, Double patterning technology, Electronic design automation, Scanners, Printing, Optical lithography

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When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brion's Tachyo^TM system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

Proceedings Article | 20 October 2006 Paper

Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20

Judy Huckabay, Wolf Staud, Robert Naber, Anton van Oosten, Peter Nikolski, Stephen Hsu, R. Socha, M. Dusa, Donis Flagello

Proceedings Volume 6349, 634910 (2006) https://doi.org/10.1117/12.687747

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Semiconducting wafers, Lithography, Neodymium, Logic, Optical lithography, Scanners, Resolution enhancement technologies

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Proceedings Article | 20 October 2006 Paper

Application challenges with double patterning technology (DPT) beyond 45 nm

Jungchul Park, Stephen Hsu, Douglas Van Den Broeke, J. Fung Chen, Mircea Dusa, Robert Socha, Jo Finders, Bert Vleeming, Anton van Oosten, Peter Nikolsky, Vincent Wiaux, Eric Hendrickx, Joost Bekaert, Geert Vandenberghe

Proceedings Volume 6349, 634922 (2006) https://doi.org/10.1117/12.692921

KEYWORDS: Photomasks, Optical lithography, Optical proximity correction, Double patterning technology, Etching, Model-based design, Printing, Manufacturing, Critical dimension metrology, Photoresist processing

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Proceedings Article | 20 May 2006 Paper

Automatic pitch decomposition for improved process window when printing dense features at k₁eff<0.20

Judy Huckabay, Wolf Staud, Robert Naber, Mircea Dusa, Donis Flagello, Robert Socha

Proceedings Volume 6283, 62830T (2006) https://doi.org/10.1117/12.681853

KEYWORDS: Photomasks, Double patterning technology, Optical proximity correction, Printing, Semiconducting wafers, Critical dimension metrology, Lithography, Feature extraction, 3D modeling, Manufacturing

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Proceedings Article | 20 May 2006 Paper

A single-exposure approach for patterning 45nm flash/DRAM contact hole mask

Ting Chen, Doug Van Den Broeke, Edita Tejnil, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep De Vocht, Noel Corcoran, J. Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6283, 62831A (2006) https://doi.org/10.1117/12.681873

KEYWORDS: Optical proximity correction, Electroluminescence, Optical lithography, Printing, Photomasks, Lithographic illumination, Semiconducting wafers, Diffractive optical elements, Manufacturing, Nanoimprint lithography

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Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k₁ conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IML^TM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

Proceedings Article | 29 March 2006 Paper

Everything you ever wanted to know about why the semiconductor industry needs a high-refractive index photoresist but were afraid to ask: Part I

Will Conley, Robert Socha

Proceedings Volume 6153, 61531L (2006) https://doi.org/10.1117/12.659656

KEYWORDS: Refractive index, Photoresist materials, Polarization, Photomasks, Photoresist developing, Semiconductors, Lithography, Water, Refraction, Polymers

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Proceedings Article | 15 March 2006 Paper

Patterning 45nm flash/DRAM contact hole mask with hyper-NA immersion lithography and optimized illumination

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Noel Corcoran, Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6154, 61541O (2006) https://doi.org/10.1117/12.656982

KEYWORDS: Electroluminescence, Semiconducting wafers, Photomasks, Diffractive optical elements, Optical lithography, Printing, Nanoimprint lithography, Optical proximity correction, Polarization, Finite element methods

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Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k₁ printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k₁ conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IML^TM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.

Proceedings Article | 8 November 2005 Paper

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Robert Socha, JungChul Park, Keith Gronlund

Proceedings Volume 5992, 599239 (2005) https://doi.org/10.1117/12.633465

KEYWORDS: Electroluminescence, Printing, Nanoimprint lithography, Lithographic illumination, Cerium, Fiber optic illuminators, Manufacturing, Optical proximity correction, Optical lithography, Photomasks

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Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k₁, e.g. k₁<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k₁<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Proceedings Article | 28 June 2005 Paper

A proposal for the contact hole assist feature printing checker in IML

Jason Shieh, Robert Socha, Xuelong Shi, Alek Chen

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617191

KEYWORDS: Printing, 3D modeling, Photomasks, Lithography, Optical imaging, Image processing, Phase shifts, Image analysis, Feature extraction, Reticles

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Proceedings Article | 28 June 2005 Paper

Simultaneous source mask optimization (SMO)

Robert Socha, Xuelong Shi, David LeHoty

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617431

KEYWORDS: Photomasks, Source mask optimization, Diffraction, Spatial frequencies, Fourier transforms, Manufacturing, Lithography, System on a chip, Constructive interference, Linear filtering

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Proceedings Article | 28 June 2005 Paper

Precision process calibration and CD predictions for low-k1 lithography

Ting Chen, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Linda Yu, Stephen Hsu, Doug van den Broeke, Robert Socha, Jungchul Park, Keith Gronlund, Todd Davis, Vince Plachecki, Tom Harris, Steve Hansen, Chuck Lambson

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617218

KEYWORDS: Calibration, 3D modeling, Process modeling, Data modeling, Diffusion, Photoresist processing, Lithography, Critical dimension metrology, Photomasks, Semiconducting wafers

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Leading resist calibration for sub-0.3 k₁ lithography demands accuracy <2nm for CD through pitch. An accurately calibrated resist process is the prerequisite for establishing production-worthy manufacturing under extreme low k₁. From an integrated imaging point of view, the following key components must be simultaneously considered during the calibration - high numerical aperture (NA>0.8) imaging characteristics, customized illuminations (measured vs. modeled pupil profiles), resolution enhancement technology (RET) mask with OPC, reticle metrology, and resist thin film substrate. For imaging at NA approaching unity, polarized illumination can impact significantly the contrast formation in the resist film stack, and therefore it is an important factor to consider in the CD-based resist calibration. For aggressive DRAM memory core designs at k₁<0.3, pattern-specific illumination optimization has proven to be critical for achieving the required imaging performance. Various optimization techniques from source profile optimization with fixed mask design to the combined source and mask optimization have been considered for customer designs and available imaging capabilities. For successful low-k₁ process development, verification of the optimization results can only be made with a sufficiently tunable resist model that can predicate the wafer printing accurately under various optimized process settings. We have developed, for resist patterning under aggressive low-k₁ conditions, a novel 3D diffusion model equipped with double-Gaussian convolution in each dimension. Resist calibration with the new diffusion model has demonstrated a fitness and CD predication accuracy that rival or outperform the traditional 3D physical resist models. In this work, we describe our empirical approach to achieving the nm-scale precision for advanced lithography process calibrations, using either measured 1D CD through-pitch or 2D memory core patterns. We show that for ArF imaging, the current resist development and diffusion modeling can readily achieve ~1-2nm max CD errors for common 1D through-pitch and aggressive 2D memory core resist patterns. Sensitivities of the calibrated models to various process parameters are analyzed, including the comparison between the measured and modeled (Gaussian or GRAIL) pupil profiles. We also report our preliminary calibration results under selected polarized illumination conditions.

Proceedings Article | 28 June 2005 Paper

RET masks for the final frontier of optical lithography

J. Chen, Douglas van den Broeke, Stephen Hsu, Michael Hsu, Tom Laidig, Xuelong Shi, Ting Chen, Robert Socha, Uwe Hollerbach, Kurt Wampler, Jungchul Park, Sangbong Park, Keith Gronlund

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617430

KEYWORDS: Photomasks, Printing, Optical proximity correction, Lithography, Resolution enhancement technologies, Optical lithography, Manufacturing, Calibration, Optics manufacturing, Model-based design

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With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k₁ close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k₁=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k₁ lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k₁ factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k₁ barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Proceedings Article | 28 June 2005 Paper

Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617165

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Performance modeling, Manufacturing, Scattering, Lithography, Semiconducting wafers, Printing, Diffractive optical elements

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Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁ lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Proceedings Article | 12 May 2005 Paper

Lithography manufacturing implementation for 65 nm and 45 nm nodes with model-based scattering bars using IML technology

Michael Hsu, Doug Van Den Broeke, Tom Laidig, Kurt Wampler, Uwe Hollerbach, Robert Socha, J. Chen, Stephen Hsu, Xuelong Shi

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598589

KEYWORDS: Photomasks, Optical proximity correction, Model-based design, Manufacturing, Lithography, Performance modeling, Scattering, Printing, Diffractive optical elements, Design for manufacturing

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Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁lithography manufacturing. ⁽¹⁾ The manufacturing implementation of SB so far has been mainly based on rule-based approach. While thiis has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML. Technology from ASML MaskTools.^(2,3) In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible for MaskWeaver to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Proceedings Article | 12 May 2005 Paper

Layout and source dependent transmission tuning

Chris Progler, Will Conley, Bob Socha, Young Ham

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.601770

KEYWORDS: Photomasks, Optimization (mathematics), Logic, Lithography, Phase shifts, Critical dimension metrology, Prototyping, Lithographic illumination, Algorithm development, Manufacturing

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Proceedings Article | 12 May 2005 Paper

The impact of illumination on feature fidelity for CPL mask technology

Jan Kuijten, Arjan Verhappen, Will Conley, Stephan van de Goor, Lloyd Litt, Wei Wu, Kevin Lucas, Bernie Roman, Bryan Kasprowicz, Chris Progler, Robert Socha, Doug van den Broeke, Kurt Wampler, Tom Laidig, Stephen Hsu

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.605481

KEYWORDS: Chromium, Photomasks, Nanoimprint lithography, Phase shifts, Resolution enhancement technologies, Optical proximity correction, Mask making, Semiconductors, Photoresist materials, Manufacturing

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SPIE Journal Paper | 1 April 2005

Extending aggressive low-k1 design rule requirements for 90 and 65 nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction

Sabita Roy, Douglas Van Den Broeke, J. Fung Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

JM3, Vol. 4, Issue 02, 023003, (April 2005) https://doi.org/10.1117/12.10.1117/1.1898244

KEYWORDS: Optical proximity correction, Diffractive optical elements, Critical dimension metrology, Calibration, Photomasks, Stanford Linear Collider, Fiber optic illuminators, Lithography, Printing, Logic

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Proceedings Article | 6 December 2004 Paper

Contact and via hole mask design optimization for 65-nm technology node

Douglas Van Den Broeke, Xuelong Shi, Robert Socha, Tom Laidig, Uwe Hollerbach, Kurt Wampler, Stephen Hsu, J. Fung Chen, Noel Corcoran, Mircea Dusa, Jung Chul Park

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568692

KEYWORDS: Reticles, Resolution enhancement technologies, Printing, Scattering, Binary data, Manufacturing, Optical proximity correction, Photomasks, Model-based design, Algorithm development

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For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k₁ for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k₁ values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k₁, it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPL^TM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IML^TM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RET's including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Proceedings Article | 6 December 2004 Paper

Mask topography effect in chromeless phase lithography

Vicky Philipsen, Joost Bekaert, Geert Vandenberghe, Rik Jonckheere, Douglas Van Den Broeke, Robert Socha

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568694

KEYWORDS: Photomasks, Etching, Chromium, Quartz, Lithography, Semiconducting wafers, Lithographic illumination, 193nm lithography, Reticles, Mask making

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Proceedings Article | 20 August 2004 Paper

CPL reticle technology for advanced device applications

Willard Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, J. Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony, Michael Hathorn

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557802

KEYWORDS: Photomasks, Optical proximity correction, Image processing, Reticles, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Quartz, Binary data

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Proceedings Article | 20 August 2004 Paper

CPL mask technology for sub-100-nm contact hole imaging

Bryan Kasprowicz, Willard Conley, Lloyd Litt, Douglas Van Den Broeke, Patrick Montgomery, Robert Socha, Wei Wu, Kevin Lucas, Bernard Roman, J. Fung Chen, Kurt Wampler, Thomas Laidig, Christopher Progler, Michael Hathorn

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557755

KEYWORDS: Photomasks, Reticles, Manufacturing, Inspection, Lithography, Image processing, Semiconducting wafers, Quartz, Metrology, Optical lithography

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Proceedings Article | 20 August 2004 Paper

Application of CPL with Interference Mapping Lithography to generate random contact reticle designs for the 65-nm node

Douglas Van Den Broeke, Thomas Laidig, J. Fung Chen, Kurt Wampler, Stephen Hsu, Xuelong Shi, Robert Socha, Mircea Dusa, Noel Corcoran

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557751

KEYWORDS: Reticles, Lithography, Resolution enhancement technologies, Manufacturing, Phase shifts, Photomasks, Printing, Lithographic illumination, Phase shifting, Semiconducting wafers

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Imaging contact and via layers continues to be one of the major challenges to be overcome for 65nm node lithography. Initial results of using ASML MaskTools' CPL Technology to print contact arrays through pitch have demonstrated the potential to further extend contact imaging to a k1 near 0.30. While there are advantages and disadvantages for any potential RET, the benefits of not having to solve the phase assignment problem (which can lead to unresolvable phase conflicts), of it being a single reticle - single exposure technique, and its application to multiple layers within a device (clear field and dark field) make CPL an attractive, cost effective solution to low k1 imaging. However, real semiconductor circuit designs consist of much more than regular arrays of contact holes and a method to define the CPL reticle design for a full chip circuit pattern is required in order for this technique to be feasible in volume manufacturing. Interference Mapping Lithography (IML) is a novel approach for defining optimum reticle patterns based on the imaging conditions that will be used when the wafer is exposed. Figure 1 shows an interference map for an isolated contact simulated using ASML /1150 settings of 0.75NA and 0.92/0.72/30deg Quasar illumination. This technique provides a model-based approach for placing all types features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary (COG), attenuated phase shifting mask (attPSM), alternating aperture phase shifting mask (altPSM), and CPL. In this work, we investigate the application of IML to generate CPL reticle designs for random contact patterns that are typical for 65nm node logic devices. We examine the critical issues related to using CPL with Interference Mapping Lithography including controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, and reticle manufacturing constraints. Multiple methods for deriving the interference map used to define reticle patterns for various RET's will be discussed. CPL reticle designs that were created from implementing automated algorithms for contact pattern decomposition using MaskWeaver will also be presented.

Proceedings Article | 20 August 2004 Paper

Contact hole reticle optimization by using interference mapping lithography (IML)

Robert Socha, Douglas Van Den Broeke, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi, Willard Conley

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557747

KEYWORDS: Photomasks, Atrial fibrillation, Binary data, Electroluminescence, Point spread functions, Lithography, Fresnel lenses, Semiconducting wafers, Phase shifts, Reticles

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Proceedings Article | 20 August 2004 Paper

Through-pitch low-k₁ contact hole imaging with CPL technology

Vincent Wiaux, Joost Bekaert, J. Fung Chen, Stephen Hsu, Kurt Ronse, Robert Socha, Geert Vandenberghe, Douglas Van Den Broeke

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557803

KEYWORDS: Reticles, Resolution enhancement technologies, Printing, Lithography, Immersion lithography, Chromium, Electroluminescence, Semiconducting wafers, Photomasks, Critical dimension metrology

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Proceedings Article | 28 May 2004 Paper

Implementation of pattern-specific illumination pupil optimization on Step & Scan systems

Andre Engelen, Robert Socha, Eric Hendrickx, Wieger Scheepers, Frank Nowak, Marco Van Dam, Armin Liebchen, Denis Faas

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.544240

KEYWORDS: Diffractive optical elements, Zoom lenses, Imaging systems, Fiber optic illuminators, Axicons, Photomasks, Manufacturing, Scanning electron microscopy, Critical dimension metrology, Optimization (mathematics)

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Proceedings Article | 28 May 2004 Paper

The impact of MEEF through pitch for 120-nm contact holes

Lloyd Litt, Wei Wu, Will Conley, Kevin Lucas, Bernard Roman, Patrick Montgomery, Bryan Kasprowicz, Christopher Progler, Robert Socha, Arjan Verhappen, Kurt Wampler, Erika Schaefer, Pat Cook, Jan-Pieter Kuijten, Wil Pijnenburg

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537437

KEYWORDS: Fiber optic illuminators, Atrial fibrillation, Critical dimension metrology, Resolution enhancement technologies, Photomasks, Semiconducting wafers, Manufacturing, Reticles, Nanoimprint lithography, Binary data

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Proceedings Article | 28 May 2004 Paper

Contact hole reticle optimization by using interference mapping lithography (IML)

Robert Socha, Douglas Van Den Broeke, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi, Will Conley

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536581

KEYWORDS: Photomasks, Atrial fibrillation, Binary data, Electroluminescence, Point spread functions, Lithography, Fresnel lenses, Semiconducting wafers, Phase shifts, Reticles

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Proceedings Article | 28 May 2004 Paper

Defect printability in CPL mask technology

Jan-Pieter Kuijten, Arjan Verhappen, Wil Pijnenburg, Will Conley, Lloyd Litt, Wei Wu, Patrick Montgomery, Bernard Roman, Bryan Kasprowicz, Christopher Progler, Robert Socha, Douglas Van Den Broeke, Erika Schaefer, Pat Cook

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537619

KEYWORDS: Photomasks, Resolution enhancement technologies, Reticles, Manufacturing, Scanning electron microscopy, Semiconductors, Phase shifts, Binary data, Lithography, Semiconducting wafers

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Proceedings Article | 28 May 2004 Paper

The application of CPL reticle technology for the 0.045-mm node

Will Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Bernard Roman, Richard Peters, Colita Parker, Fung Chen, Kurt Wampler, Thomas Laidig, Erika Schaefer, Jan-Pieter Kuijten, Arjan Verhappen, Stephan van de Goor, Martin Chaplin, Bryan Kasprowicz, Christopher Progler, Emilien Robert, Philippe Thony

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537613

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Image processing, Resolution enhancement technologies, Phase shifts, Mask making, Scanning electron microscopy, Manufacturing, Quartz

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Proceedings Article | 28 May 2004 Open Access

Optical lithography in the sub-50-nm regime

Donis Flagello, Bill Arnold, Steve Hansen, Mircea Dusa, Robert Socha, Jan Mulkens, Reiner Garreis

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535432

KEYWORDS: Polarization, Reticles, Photoresist materials, Photomasks, Chromium, Optical lithography, Semiconducting wafers, Sodium, Resolution enhancement technologies, Lithography

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Proceedings Article | 3 May 2004 Paper

Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC

Sabita Roy, Douglas Van Den Broeke, J. Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.536982

KEYWORDS: Diffractive optical elements, Optical proximity correction, Calibration, Critical dimension metrology, Stanford Linear Collider, Photomasks, Fiber optic illuminators, Printing, Logic, Lithography

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Under low-k₁ patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k₁ imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k₁ factor for the three types of circuits. For 90nm node with k₁ as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.

Proceedings Article | 17 December 2003 Paper

Near-0.3 k1 full pitch range contact hole patterning using chromeless phase lithography (CPL)

Douglas Van Den Broeke, Robert Socha, Stephen Hsu, J. Fung Chen, Thomas Laidig, Noel Corcoran, Uwe Hollerbach, Kurt Wampler, Xuelong Shi

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518308

KEYWORDS: Reticles, Printing, Resolution enhancement technologies, Manufacturing, Lithography, Semiconducting wafers, Lithographic illumination, Optical lithography, Phase shifts, Scanners

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Proceedings Article | 26 June 2003 Paper

ArF solutions for low-k₁ back-end imaging

Vincent Wiaux, Patrick Montgomery, Geert Vandenberghe, Philippe Monnoyer, Kurt Ronse, Will Conley, Lloyd Litt, Kevin Lucas, Jo Finders, Robert Socha, Douglas Van Den Broeke

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485502

KEYWORDS: Electroluminescence, Printing, Resolution enhancement technologies, Photomasks, Lithography, Reticles, Optical lithography, Phase shifts, Lithographic illumination, Metrology

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The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k₁ regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k₁ range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k₁, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

Proceedings Article | 26 June 2003 Paper

65-nm full-chip implementation using double dipole lithography

Stephen Hsu, J. Fung Chen, Noel Cororan, William Knose, Douglas Van Den Broeke, Thomas Laidig, Kurt Wampler, Xuelong Shi, Michael Hsu, Mark Eurlings, Jo Finders, Tsann-Bim Chiou, Robert Socha, Will Conley, Yen Hsieh, Steve Tuan, Frank Hsieh

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485445

KEYWORDS: Reticles, Photomasks, Model-based design, Scattering, Optical proximity correction, Stray light, Resolution enhancement technologies, 3D modeling, Logic, Binary data

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Proceedings Article | 26 June 2003 Paper

Application of CPL reticle technology for the 65- and 50-nm node

Will Conley, Douglas Van Den Broeke, Robert Socha, Wei Wu, Lloyd Litt, Kevin Lucas, Carla Nelson-Thomas, Bernard Roman, J. Fung Chen, Kurt Wampler, Thomas Laidig, Stephen Hsu, Erika Schaefer, Shawn Cassel, Linda Yu, Bryan Kasprowicz, Christopher Progler, John Petersen, David Gerold, Mark John Maslow

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485515

KEYWORDS: Photomasks, Reticles, Optical proximity correction, Image processing, Resolution enhancement technologies, Manufacturing, Phase shifts, Mask making, Quartz, Lithography

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Proceedings Article | 26 June 2003 Paper

Mighty high-T lithography for 65-nm generation contacts

Will Conley, Patrick Montgomery, Kevin Lucas, Lloyd Litt, John Maltabes, Laurent Dieu, Gregory Hughes, David Mellenthin, Robert Socha, Eric Fanucchi, Arjan Verhappen, Kurt Wampler, Linda Yu, Erika Schaefer, Shawn Cassel, Jan Kuijten, Wil Pijnenburg, Vincent Wiaux, Geert Vandenberghe

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485499

KEYWORDS: Photomasks, Lithography, Inspection, Reticles, Optical lithography, Lithographic illumination, Binary data, Manufacturing, 193nm lithography, Semiconducting wafers

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Proceedings Article | 26 June 2003 Paper

Optimizing and enhancing optical systems to meet the low k₁ challenge

Donis Flagello, Robert Socha, Xuelong Shi, Jan van Schoot, Jan Baselmans, Mark van de Kerkhof, Wim de Boeij, Andre Engelen, Rene Carpaij, Oscar Noordman, Marco Moers, Melchior Mulder, Jo Finders, Henk van Greevenbroek, Martin Schriever, Manfred Maul, Helmut Haidner, Markus Goeppert, Ulrich Wegmann, Paul Graeupner

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485340

KEYWORDS: Lithographic illumination, Reticles, Wavefronts, Sensors, Semiconducting wafers, Light scattering, Lithography, Critical dimension metrology, Scanners, Control systems

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Proceedings Article | 27 December 2002 Paper

Advanced 193 tri-tone EAPSM (9% to 18%) for 65-nm node

Laurent Dieu, Eric Fanucchi, Greg Hughes, John Maltabes, David Mellenthin, Will Conley, Lloyd Litt, Kevin Lucas, Robert Socha, Kurt Wampler, Arjan Verhappen, Jan-Pieter Kiujten

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467783

KEYWORDS: Reticles, Inspection, Multilayers, Tin, Manufacturing, Lithography, Etching, Photomasks, Process control, Transmittance

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Proceedings Article | 27 December 2002 Paper

Mesa or trench type for chromeless phase-shift lithography from photolithographic performance point of view

Xuelong Shi, J. Fung Chen, Stephen Hsu, Michael Hsu, Douglas Van Den Broeke, Robert Socha, Chun Hong Chang, Chang Min Dai

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467393

KEYWORDS: Photomasks, Phase shifts, Optical lithography, Diffraction, Lithography, 3D image processing, Quartz, Etching, Electromagnetism, Optical proximity correction

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Proceedings Article | 27 December 2002 Paper

Application of chromeless phase lithography (CPL) masks in ArF lithography

Bryan Kasprowicz, Christopher Progler, Wei Wu, Will Conley, Lloyd Litt, Douglas Van Den Broeke, Kurt Wampler, Robert Socha

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468107

KEYWORDS: Photomasks, Lithography, Quartz, Etching, Manufacturing, Reticles, Inspection, Antireflective coatings, Optical proximity correction, Binary data

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SPIE Journal Paper | 1 October 2002

Complex two dimensional pattern lithography using chromeless phase lithography (CPL)

Douglas Van Den Broeke, J. Fung Chen, Thomas Laidig, Stephen Hsu, Kurt Wampler, Robert Socha, John Petersen

JM3, Vol. 1, Issue 03, (October 2002) https://doi.org/10.1117/12.10.1117/1.1504458

KEYWORDS: Reticles, Lithography, Semiconducting wafers, Manufacturing, Optical lithography, Lithographic illumination, Resolution enhancement technologies, Opacity, Printing, Scanning electron microscopy

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