In advanced lithography, controlling overlay budget is critical, and how to control on production overlay(OPO) quality well as 100% measurement sampling in high volume manufacturing fab will be an impossible mission. Nevertheless, most of HVM fabs encounter with almost the same problem for low sampling lot, wafers, even less measurement points by reason of facility and Fab space issue and cost. No matter how critical overlay need, the advanced process correction (APC) maintaining the overlay performance under 10%~15% lot base sampling with 4 wafers may be the limitation in most of HVM fabs. Base on the 100% measurement conception and possibility, CXMT begin to study ASML cMetro (computation Metrology) possibility through measuring uDBO in Yield Star and combining with scanner leveling information, coming to catch overlay issue wafers and make sure overlay quality as 100% sampling measurement. To achieve this, conventionally, users try to study process possibility in leveling information between with overlay behaviors under the immersion critical layers. To identify the layer strategy and program successful, how to input and build-up cMetro modeling is reasonable and the monitor result is anticipated catching inline overly issue lots under cMetro prediction will be vitally important, no matter going through scanner leveling data method or combining with uDBO measurement as HDOM model. However, this approach will be time-consuming in the beginning due to not only several leveling condition and spilt are necessary, but also need to collect SSO (sampling scheme optimization) or sparse map and high dense map in uDBO measurement. Aiming to speed up the turnaround time, CXMT focus on layers with warpage experience and define the lots & wafers & map sampling to find the correlation. As a results, cMetro HDOM model monitor is possibility to hold up the issue overlay lots even under real inline measurement sampling for 10~15%.
Advancing technology nodes in DRAM continues to drive the reduction of on-product overlay (OV) budget. This gives rise to the need for OV metrology with greater accuracy. However, the ever increasing process complexity brings additional challenges related to metrology target deformation, which could contribute to a metrology error. Typically, an accurate OV measurement involves several engineering cycles for target and recipe optimization. In particular, process optimization in either technology development (TD) phase or high volume manufacturing (HVM) phase might influence metrology performance, which requires re-optimization. Therefore, a comprehensive solution providing accuracy and process robustness hereby minimizing the cycle time is highly desirable. In this work, we report multi-wavelength µDBO enhanced with accuracy aware pixel selection as a solution for robust OV measurement against process changes as well as improved accuracy in HVM. Accuracy aware pixel selection is capable of tackling intra-target processing variations and is established on a multi-wavelength algorithm with immunity to target asymmetry impact. DRAM use cases in FEOL critical layers will be discussed in this paper. Superior robustness and accuracy will be demonstrated together with improved on-product OV performance, promising a process of record metrology solution in specific applications throughout the TD and HVM.
During wafer exposure, the scanner overlays product structures from the layer being exposed onto underlying layers, with a limited error margin. Alignment is the process of measuring pre-defined marks that have been exposed on previous layers and using these measurements to determine what adjustments to make during exposure. Current alignment marks are still quite big compared to overlay targets and fill quite some reticle-area. Therefore, there is a drive towards narrower and smaller alignment marks in order to free up scribe-lane space. Further, during design of narrower and/or smaller alignment marks, not only the width or length needs to be taken into account, but also the process loading effect and scribe-lane dummy following rules.
Maximizing product-area is an important driver for many DRAM customers. One way is by reducing scribe-lane space. Currently most customers are using 60um to 90 um wide scribe-lanes. However, developments are ongoing to further reduce this to 40um -50um. The current narrowest standard ASML alignment marks are 40 um wide and there is a growing demand for narrower and even smaller marks. Experiment tool groups configure selection with ASML SMASH senor and it brings more possibility in scribe-lane design and alignment size topic.
Tests with narrow alignment marks were done on an ASML XT1460K scanner with SMASH3.1 sensor. Both narrow DPCM (coarse align) and narrow NSSM marks (coarse and fine align) were tested and the impact on accuracy, repro and overlay was investigated. The width of the DPCM marks was reduced from 160um to 150um and 140um. The width of the NSSM (AA11 and AH53) marks was reduced from 40um to 30um and 28um.
This paper will explain the tests done in detail and will present the results of using narrow marks on alignment mark repro, mark KPIs (WQ, MCC, etc.) and overlay performance. These results will be compared to those of the standard marks. Also results from further alignment mark recipe optimization will be presented.
In order to achieve better resolution and improve lithography process window, device manufacturers are looking into or adopting high transmission attenuated phase shift mask (HTM). The critical dimension uniformity (CDU) of the device pattern can be quite a bit better with high transmission mask as compared to conventional attenuated phase shift mask, which makes it an attractive choice for advanced memory devices. However, it poses challenges on metrology targets such as alignment marks or micro diffraction-based overlay (uDBO) marks, which has different dimensions as device patterns as required by the metrology sensors. The challenges include printability, detectability, accuracy, process compatibility and defectively on the same device layer. In this paper we demonstrate solutions to address these challenges and thereby improve metrology for advanced memory devices with HTM. Without sacrificing mark contrast on wafer, the wafer quality of alignment mark is improved up to 10 times with respect to array like alignment marks and the stack sensitivity of uDBO mark can also increase more than 7 times as array like marks. Through a holistic target approach involving target design, target OPC, and recipe setup, we are able to achieve accurate metrology for optimal on-product overlay and device yield.
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