Dr. Jochen Schacht Profile

Dr. Jochen Schacht

at Infineon Technologies AG

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Author

Publications (5)

Proceedings Article | 26 March 2007 Paper

SEM based data extraction for model calibration

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, George Bailey, Te Hung Wu, Chia Wei Huang, Sheng Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6520, 65203B (2007) https://doi.org/10.1117/12.707353

KEYWORDS: Data modeling, Scanning electron microscopy, Calibration, Process modeling, Image processing, Optical proximity correction, Semiconducting wafers, Metrology, Resolution enhancement technologies, Feature extraction

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The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

Proceedings Article | 21 March 2007 Paper

A systematic approach for capturing interconnects hot spots

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, Te Hung Wu, Chia Wei Huang, Shen Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6521, 65211C (2007) https://doi.org/10.1117/12.713521

KEYWORDS: Semiconducting wafers, Photomasks, Image processing, Overlay metrology, Integrated circuits, Lithography, Resistance, Classification systems, Integrated circuit design, Transistors

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Proceedings Article | 28 May 2004 Paper

Specification of the phase angle of a 6% attenuated PSM mask used in ArF lithography

Ching-Hsu Chang, Jochen Schacht, Benjamin Lin, Kuei-Chun Hung, I. Hsuing Huang

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535167

KEYWORDS: Critical dimension metrology, Photomasks, Image transmission, Reticles, Lithography, Phase shifts, Scanning electron microscopy, Binary data, Monochromatic aberrations, Transmittance

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Proceedings Article | 28 May 2004 Paper

Calibration of OPC models for multiple focus conditions

Jochen Schacht, Klaus Herold, Rainer Zimmermann, J. Andres Torres, Wilhelm Maurer, Yuri Granik, Ching-Hsu Chang, G. Kuei-Chun Hung, Benjamin Szu-Min Lin

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534123

KEYWORDS: Calibration, Data modeling, Process modeling, Optical proximity correction, Photoresist processing, Image processing, Metrology, Thin films, Image acquisition, Error analysis

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Proceedings Article | 14 May 2004 Paper

Optimization of resist shrink techniques for contact hole and metal trench ArF lithography at the 90-nm technology node

Christine Wallace, Jochen Schacht, I Huang, Ruei Hsu

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.534610

KEYWORDS: Photoresist processing, Critical dimension metrology, Glasses, Lithography, Semiconducting wafers, Etching, Line edge roughness, Scanning electron microscopy, Metals, Reticles

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Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.

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