Dr. Rainer Zimmermann Profile

Dr. Rainer Zimmermann

at Synopsys GmbH

SPIE Involvement:

Author

Publications (13)

Proceedings Article | 17 October 2023 Presentation + Paper

Optical and manufacturing design aware flow for metalenses

M. Chalony, B. Küchler, R. Zimmermann, C. Xu, L. Melvin, E. Viasnoff

Proceedings Volume 12741, 1274105 (2023) https://doi.org/10.1117/12.3000524

KEYWORDS: Manufacturing, Design and modelling, Etching, Metalenses, Optics manufacturing, Lithography

Read Abstract +

Proceedings Article | 5 October 2023 Paper

Efficient mask characterization through automated contour and corner rounding extraction

Rainer Zimmermann, Joost Bekaert, Mariya Braylovska, Balakumar Baskaran, Vicky Philipsen, Martin Bohn, Michael Bachmann, Ulrich Klostermann, Eric Hendrickx, Wolfgang Demmerle

Proceedings Volume 12802, 128020J (2023) https://doi.org/10.1117/12.2675486

KEYWORDS: Scanning electron microscopy, Contour extraction, Lithography, Semiconducting wafers, Critical dimension metrology, Calibration, Image quality, Contour modeling, Mask making

Read Abstract +

Proceedings Article | 1 May 2023 Presentation + Paper

Computational patterning and process variation impact on photonics devices

Maryvonne Chalony, Lawrence Melvin, Rainer Zimmermann, Bernd Küchler, Emilie Viasnoff, Robert Scarmozzino, Daniel Herrmann, Yves Saad, Phil Stopford, Thuc Dam, Ulrich Klostermann, Wolfgang Demmerle, Al Blais, Remco Stoffer

Proceedings Volume 12499, 124990A (2023) https://doi.org/10.1117/12.2658788

KEYWORDS: Design and modelling, Manufacturing, Polarization, Optics manufacturing, Photonic devices, Optical lithography, Incident light, Metalenses, Geometrical optics, Optical proximity correction

Read Abstract +

Proceedings Article | 26 May 2022 Presentation + Paper

Mask synthesis for silicon photonics devices

Rainer Zimmermann, Luis Orbe, Bernd Küchler, Ji Li, Jim Burdorf, William Stanton, Tung-Yu Su, Remco Stoffer, Ulrich Klostermann, Wolfgang Demmerle

Proceedings Volume 12148, 1214809 (2022) https://doi.org/10.1117/12.2620724

KEYWORDS: Optical proximity correction, Photomasks, Waveguides, Photonic devices, Lithography, Line edge roughness, Stochastic processes, Photonics, Signal to noise ratio

Read Abstract +

Proceedings Article | 28 March 2014 Paper

Layout optimization of DRAM cells using rigorous simulation model for NTD

Jinhyuck Jeon, Shinyoung Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Bernd Kuechler, Rainer Zimmermann, Thomas Muelders, Ulrich Klostermann, Thomas Schmoeller, Mun-hoe Do, Jung-Hoe Choi

Proceedings Volume 9053, 90530J (2014) https://doi.org/10.1117/12.2046541

KEYWORDS: Photomasks, Optical proximity correction, SRAF, Printing, Semiconducting wafers, 3D modeling, Calibration, Optimization (mathematics), Source mask optimization, Manufacturing

Read Abstract +

DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.

Proceedings Article | 8 November 2012 Paper

Proximity effect correction optimizing image quality and writing time for an electron multi-beam mask writer

T. Klimpel, J. Klikovits, R. Zimmermann, M. Schulz, Alex Zepka, H.-J. Stock

Proceedings Volume 8522, 852229 (2012) https://doi.org/10.1117/12.964405

KEYWORDS: Image quality, Photomasks, Scanning electron microscopy, Nanoimprint lithography, Backscatter, Modulation, Acquisition tracking and pointing, Ions, Metals, Line width roughness

Read Abstract +

Proceedings Article | 23 September 2009 Paper

Predictive modeling for EBPC in EBDW

Rainer Zimmermann, Martin Schulz, Wolfgang Hoppe, Hans-Jürgen Stock, Wolfgang Demmerle, Alex Zepka, Artak Isoyan, Lars Bomholt, Serdar Manakli, Laurent Pain

Proceedings Volume 7488, 74883J (2009) https://doi.org/10.1117/12.833482

KEYWORDS: Data modeling, 3D modeling, Electron beam direct write lithography, Point spread functions, Critical dimension metrology, Model-based design, Geometrical optics, Cadmium, Error analysis, Virtual reality

Read Abstract +

Proceedings Article | 21 March 2007 Paper

Ensuring production-worthy OPC recipes using large test structure arrays

Christopher Cork, Rainer Zimmermann, Xin Mei, Alexander Shahin

Proceedings Volume 6521, 65211D (2007) https://doi.org/10.1117/12.713411

KEYWORDS: Optical proximity correction, Critical dimension metrology, Manufacturing, Lithography, Tolerancing, Photomasks, Design for manufacturability, Product engineering, Semiconductors, Control systems

Read Abstract +

The continual shrinking of design rules as the industry follows Moore's Law and the associated need for low k1 processes, have resulted in more layout configurations becoming difficult to print within the required tolerances. OPC recipes have needed to become more complex as tolerances decreased and acceptable corrections harder to find with simple algorithms. With this complexity comes the possibility of coding errors and ensuring the solutions are truly general. OPC Verification tools can check the quality of a correction based on pre-determined specifications for CD variation, line-end pullback and Edge Placement Error and then highlight layout configuration where violations are found. The problem facing a Mask Tape-Out group is that they usually have little control over the Design Styles coming in. Different approaches to eliminating problematic layouts have included highly restrictive Design Rules [1], whereby certain pitches or orientations are disallowed. Now these design rules are either becoming too complex or they overly restrict the designer from benefiting from the reduced pitch of the new node. The tight link between Design and Mask Tape-Out found in Integrated Device Manufacturers [2] (IDMs) i.e. companies that control both design and manufacturing can do much to dictate manufacturing friendly layout styles, and push ownership of problem resolution back to design groups. In fact this has been perceived as such an issue that a new class of products for designers that perform Lithographic Compliance Check on design layout is an emerging technology [3]. In contrast to IDMs, Semiconductor Foundries are presented with a much larger variety of design styles and a set of Fabless customers who generally are less knowledgeable in terms of understanding the impact of their layout on manufacturability and how to correct issues. The robustness requirements of a foundry's OPC correction recipe, therefore needs to be greater than that for an IDM's tape-out group. An OPC correction recipe which gives acceptable verification results, based solely on one customer GDS is clearly not sufficient to guarantee that all future tape-outs from multiple customers will be similarly clean. Ad hoc changes made in reaction to problems seen at verification are risky, while they may solve one particular layout issue on one product there is no guarantee that the problem may simply shift to another configuration on a yet to be manufactured part. The need to re-qualify a recipe over multiple products at each recipe change can easily results in excessive computational requirements. A single layer at an advanced node typically needs overnight runs on a large processor farm. Much of this layout, however, is extremely repetitive, made from a few standard cells placed tens of thousands of times. An alternative and more efficient approach, suggested by this paper as a screening methodology, is to encapsulate the problematic structures into a programmable test structure array. The dimensions of these test structures are parameterized in software such that they can be generated with these dimensions varied over the space of the design rules and conceivable design styles. By verifying the new recipe over these test structures one could more quickly gain confidence that this recipe would be robust over multiple tape-outs. This paper gives some examples of the implementation of this methodology.

Proceedings Article | 28 May 2004 Paper

Detailed process analysis for sub-resolution assist features introduction

Andreas Torsy, Olivier Toublan, Rainer Zimmermann, Harry Smyth, Jens Hassmann

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536575

KEYWORDS: SRAF, Optical proximity correction, Printing, Photomasks, Calibration, Model-based design, Data modeling, Visualization, Process modeling, Silicon

Read Abstract +

Sub-Resolution Assists Features (SRAF) is a well known and well described method for process window improvement. The introduction of such a technique is not always an easy task for two reasons. On one hand the SRAF placement rules must be defined very well and on the other hand an empirical resist model must be created, which describes the process. Model based Optical and Process effects correction (MB-OPC) is using an empirical model so called black box, which must be able to predict properly the printing feature for any kind of complex design configuration. When SRAF are implemented in the design, the degree of freedom for the MB-OPC can be reduced. Beside that effort to predetermine as required as possible the target layer, SRAF placement rules and SRAF printing restrictions will limit the OPC. MB-OPC has to cover both the parameters space corresponding to areas in which SRAF are placed and the parameter space for which no SRAF has been implemented. Of course, it could also be possible to apply the correction of the proximity effect of a complex design with SRAF by an extensive rule-based OPC. Nevertheless the advantage of MB-OPC exists in the possibility to verify the design after Data Preparation by simulating it with the help of the calibrated model. However one should not trust the simulation alone, always a verification of the design on silicon would be necessary, by comparing simulation to SEM images. Beside the advantages of MB-OPC also weaknesses exist in the meantime, which could require a combination of rule-based and model-based OPC, so called “hybrid OPC”. Empirical models are very often only able to predict the proximity behavior due to a certain range, which is called the optical range of a model. Distances bigger than this range will be covered by extrapolations. This procedure would be correct, if the proximity behavior was as constant as in the area inside the optical range. We generated an empirical model with the Calibre Workbench from Mentor Graphics. For the model calibration we chose structures with SRAF placement rules, which we applied to the design as well as SRAF placement rules which were not applied to the design. Afterwards, we performed simulations of critical lines over pitch including SRAF. Beside the MB-OPC, we will also describe in this paper the process steps how to generate the SRAF placement rules. The restrictions resulting from the SRAF rules are presented. Subsequently, the experimental results will show that both for symmetrical and asymmetrical structures an improvement of the process window has been obtained. Also weaknesses become clear, which place either the model or the SRAF rule-set questionable. Finally two solutions will be compared, a pure MB-OPC including the isolated lines outside of the optical range and a combination of MB-OPC with a rule-based OPC table for the isolated lines.

Proceedings Article | 28 May 2004 Paper

Calibration of OPC models for multiple focus conditions

Jochen Schacht, Klaus Herold, Rainer Zimmermann, J. Andres Torres, Wilhelm Maurer, Yuri Granik, Ching-Hsu Chang, G. Kuei-Chun Hung, Benjamin Szu-Min Lin

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.534123

KEYWORDS: Calibration, Data modeling, Process modeling, Optical proximity correction, Photoresist processing, Image processing, Metrology, Thin films, Image acquisition, Error analysis

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Model-based OPC considering process window aspects: a study

Steffen Schulze, O'Seo Park, Rainer Zimmermann, Ming-Jui Chen, Pat LaCour, Emile Sahouria, Yuri Granik, Nicolas Cobb

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474489

KEYWORDS: Optical proximity correction, Image processing, Process modeling, Lithography, Model-based design, Visualization, Resolution enhancement technologies, Phase shifting, Photomasks, Detection and tracking algorithms

Read Abstract +

Proceedings Article | 26 July 1999 Paper

Application of a new approach to optical proximity correction

Anja Rosenbusch, Andrew Hourd, Casper Juffermans, Hartmut Kirsch, Frederic Lalanne, Wilhelm Maurer, Carmelo Romeo, Kurt Ronse, Patrick Schiavone, Michal Simecek, Olivier Toublan, Tom Vermeulen, John Watson, Wolfram Ziegler, Rainer Zimmermann

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354378

KEYWORDS: Optical proximity correction, Etching, Semiconducting wafers, Inspection, Deep ultraviolet, Reticles, Critical dimension metrology, Manufacturing, Mathematical modeling, Mask making

Read Abstract +

Proceedings Article | 18 December 1998 Paper

New approach to optical proximity correction

Proceedings Volume 3546, (1998) https://doi.org/10.1117/12.332856

KEYWORDS: Optical proximity correction, Reticles, Photomasks, Inspection, Data modeling, Manufacturing, Deep ultraviolet, Logic, Semiconducting wafers, Etching

Read Abstract +

Showing 5 of 13 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years