Mr. Ryotaro Takahashi Profile

Ryotaro Takahashi

at Ushio Inc

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SPIE Journal Paper | 9 February 2024

Development of panel-level organic lithography equipment for advanced packaging

Naoya Sohara, Yu Abe, Sho Yamauchi, Ryotaro Takahashi, Hirosuke Takamatsu

JM3, Vol. 23, Issue 01, 011005, (February 2024) https://doi.org/10.1117/12.10.1117/1.JMM.23.1.011005

KEYWORDS: Lithography, Copper, Overlay metrology, Optical alignment, Optical lithography, Thermal deformation, Deformation, Film thickness, Etching, Miniaturization

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BackgroundHeterogeneous integration has been used to enhance functionality and improve operation performance by integrating separately manufactured components into system in package. To realize this high density and high performance system, continuous miniaturization is required for Cu interconnect wiring on an organic substrate.AimThe aim is to clarify the lithography issues for 5 μm L/S Cu wiring formation in the next generation. Lithographic performances, such as resolution, depth of focus (DOF), and overlay accuracy, are evaluated on an organic substrate, and the improvement of lithographic process margin is also investigated. Here, the exposure field of stepper is wide, that is, 62500 mm2.ApproachThe DOF is calculated and evaluated based on the negative dry film resist with thickness of 15 μm. Overlay accuracy was measured, using a multipoint alignment procedure.Result and ConclusionFirst result is patterning. For realizing 5 μm L/S Cu wiring in semi-additive process, resist patterning of 3.5/6.5 or 3/7 μm L/S is required due to seed Cu layer etching. Under two projection optics conditions (lens C: 5 μm L/S resolution and lens D: 3 μm L/S resolution), the process margin values of 3.5/6.5 and 3/7 μm L/S were evaluated. It was found that the process margin of 3.5/6.5 μm L/S is ±40 μm (lens C)/ ±30 μm (lens D), and the process margin of 3/7 μm L/S is ±10 μm (lens C) ±20 μm (lens D). These process margin values are enough for 5 μm L/S Cu wiring formation. And the second result is overlay. The overlay of the lithography equipment is 1.0 μm or less for deformed substrates while maintaining productivity by simultaneous multipoint measurement.

Proceedings Article | 23 March 2020 Paper

Investigating the fine line lithography process on the large-size organic panels for advanced packaging and development

Naoya Sohara, Ryotaro Takahashi, Hirosuke Takamatsu

Proceedings Volume 11327, 113270N (2020) https://doi.org/10.1117/12.2551577

KEYWORDS: Packaging, Optical lithography, Lithography, Copper, Silicon, Semiconductors, Scanning electron microscopy, Photomasks, Metals, Wet etching

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Up to now, Miniaturization has been the main drive for improving the performance of semiconductors. And higher performance of semiconductor has been the drive for applications. But miniaturization has become increasingly difficult due to increased power consumption and variations in characteristics. In order to solve these problems, by not only miniaturization of semiconductor elements, but also heterogeneous integration of the IC chips with advanced packaging technology, the higher performance and functionality improvement of the entire system has been proposed and developed. For example, the integrated SoC of the GPU and the High Bandwidth Memory (HBM) via Silicon-interposer(2.5D) are manufactured for high-performance computing, like machine learning and deep learning. With this flow, the wiring of the organic substrate package is also becoming finer line. Furthermore, it is necessary to increase the size of the die. In the following packaging trend, requiring of the Lithography equipment and process for advanced packaging is not only fine wiring to integrate but also large area exposure. In this presentation, we will show the exposure results of various dry film resist by the panel-size lithography system and inspect the state of resolution. The shot size of the lithography system is 250*250mm. Finally, we will discuss the next lithography system and process from the perspective of lithography optics and process.

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