Plasmonic technology has attracted intense research interest enhancing the functional portfolio of photonic integrated circuits (PICs) by providing Surface-Plasmon-Polariton (SPP) modes with ultra-high confinement at sub-wavelength scale dimensions and as such increased light matter interaction. However, in most cases plasmonic waveguides rely mainly on noble metals and exhibit high optical losses, impeding their employment in CMOS processes and their practical deployment in highly useful PICs. Hence, merging CMOS compatible plasmonic waveguides with low-loss photonics by judiciously interfacing these two waveguide platforms appears as the most promising route towards the rapid and costefficient manufacturing of high-performance plasmo-photonic integrated circuits. In this work, we present butt-coupled plasmo-photonic interfaces between CMOS compatible 7μm-wide Aluminum (Al) and Copper (Cu) metal stripes and 360×800nm Si3N4 waveguides. The interfaces have been designed by means of 3D FDTD and have been optimized for aqueous environment targeting their future employment in biosensing interferometric arrangements, with the photonic waveguides being cladded with 660nm of Low Temperature Oxide (LTO) and the plasmonic stripes being recessed in a cavity formed between the photonic waveguides. The geometrical parameters of the interface will be presented based on detailed simulation results, using experimentally verified plasmonic properties for the employed CMOS metals. Numerical simulations dictated a coupling efficiency of 53% and 68% at 1.55μm wavelength for Al and Cu, respectively, with the plasmonic propagation length Lspp equaling 66μm for Al and 75μm for Cu with water considered as the top cladding. The proposed interface configuration is currently being fabricated for experimental verification.
Analog optical fronthaul for 5G network architectures is currently being promoted as a bandwidth- and energy-efficient technology that can sustain the data-rate, latency and energy requirements of the emerging 5G era. This paper deals with a new optical fronthaul architecture that can effectively synergize optical transceiver, optical add/drop multiplexer and optical beamforming integrated photonics towards a DSP-assisted analog fronthaul for seamless and medium-transparent 5G small-cell networks. Its main application targets include dense and Hot-Spot Area networks, promoting the deployment of mmWave massive MIMO Remote Radio Heads (RRHs) that can offer wireless data-rates ranging from 25Gbps up to 400Gbps depending on the fronthaul technology employed. Small-cell access and resource allocation is ensured via a Medium-Transparent (MT-) MAC protocol that enables the transparent communication between the Central Office and the wireless end-users or the lamp-posts via roof-top-located V-band massive MIMO RRHs. The MTMAC is analysed in detail with simulation and analytical theoretical results being in good agreement and confirming its credentials to satisfy 5G network latency requirements by guaranteeing latency values lower than 1 ms for small- to midload conditions. Its extension towards supporting optical beamforming capabilities and mmWave massive MIMO antennas is discussed, while its performance is analysed for different fiber fronthaul link lengths and different optical channel capacities. Finally, different physical layer network architectures supporting the MT-MAC scheme are presented and adapted to different 5G use case scenarios, starting from PON-overlaid fronthaul solutions and gradually moving through Spatial Division Multiplexing up to Wavelength Division Multiplexing transport as the user density increases.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
Towards achieving a functional RAM organization that reaps the advantages offered by optical technology, a complete set of optical peripheral modules, namely the Row (RD) and Column Decoder (CD) units, is required. In this perspective, we demonstrate an all-passive 2×4 optical RAM RD with row access operation and subsequent all-passive column decoding to control the access of WDM-formatted words in optical RAM rows. The 2×4 RD exploits a WDM-formatted 2-bit-long memory WordLine address along with its complementary value, all of them encoded on four different wavelengths and broadcasted to all RAM rows. The RD relies on an all-passive wavelength-selective filtering matrix (λ-matrix) that ensures a logical ‘0’ output only at the selected RAM row. Subsequently, the RD output of each row drives the respective SOA-MZI-based Row Access Gate (AG) to grant/block the entry of the incoming data words to the whole memory row. In case of a selected row, the data word exits the row AG and enters the respective CD that relies on an allpassive wavelength-selective Arrayed Waveguide Grating (AWG) for decoding the word bits into their individual columns. Both RD and CD procedures are carried out without requiring any active devices, assuming that the memory address and data word bits as well as their inverted values will be available in their optical form by the CPU interface. Proof-of-concept experimental verification exploiting cascaded pairs of AWGs as the λ-matrix is demonstrated at 10Gb/s, providing error-free operation with a peak power penalty lower than 0.2dB for all optical word channels.
Surface plasmons polaritons are electromagnetic waves propagating along the surface of a conductor. Surface plasmons photonics is a promising candidate to satisfy the constraints of miniaturization of optical interconnects. This contribution reviews an experimental parametric study of dielectric loaded surface plasmon waveguides ring resonators and add-drop filters within the perspective of the recently suggested hybrid technology merging plasmonic and silicon photonics on a single board (European FP7 project PLATON "Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects"). Conclusions relevant for dielectric loaded surface plasmon switches to be integrated in silicon photonic circuitry will be drawn. They rely on the opportunity offered by plasmonic circuitry to carry optical signals and electric currents through the same thin metal circuitry. The heating of the dielectric loading by the electric current enables to design low foot-print thermo-optical switches driving the optical signal flow.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.